Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.

A management server includes a memory, and at least one processor configured to control an audio client system, by execution of instructions stored in the memory. The at least one processor is configured to acquire a first transfer function measured for a portion of or for all of the first signal path in the audio client system. The at least one processor is also configured to generate a virtual second signal path for a portion of or for all of the first signal path in the audio client system, and calculate a second transfer function for a portion of or for all of the generated virtual second signal path. The at least one processor is also configured to determine a condition of the audio client system, based on a result of a comparison between the first transfer function and the second transfer function.

A data transmission method applied to an APB bridge for connecting an APB and an AHB, includes: dividing transmission into an address phase and a data phase according to a feature of an AHB; in the address phase, when the AHB meets an address transmission condition corresponding to a current operation, transmitting address information and control information, which are sent by the AHB, to an APB; and in the data phase, when the APB meets a valid data transmission condition corresponding to the current operation, sending received data to a bus corresponding to the current operation, wherein the bus is the APB or the AHB. According to the present application, the address information, the control information, and the data do not need to be cached, whereby the occupation of a storage space is reduced. Further disclosed are a data transmission apparatus and an electronic device having the above beneficial effects.

Methods and apparatus for efficient data transmit and receive operations using polling of memory queues associated with interconnect fabric interface. In one embodiment, Non-Transparent Bridge (NTB) technology used to transact the data transmit/receive operations and a hardware accelerator card used implement a notification mechanism in order to optimize of receive queue polling are disclosed. The accelerator card comprises a notification address configured to signal the presence of data, and a notification acknowledgement region configured to store flags associated with memory receive queues. In one implementation, the interconnect fabric is based on PCIe technology, including up to very large fabrics and numbers of hosts/devices for use in ultra-high performance applications such as for example data centers and computing clusters.

A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

An adapter device communicates with a sink device and a source device using first and second communication schemes, respectively. The adapter device includes: a transceiver receiving a state read request by detecting that a serial data line connected between the adapter device and the sink device is driven to a low level when a serial clock line connected therebetween is at a high level, and drive the serial data line to the low level and drive the serial clock line to a low level; a transmitter transmitting the state read request to the source device after the serial clock line is driven to the low level; and a receiver receiving a state read signal to read data of a state register in the sink device from the source device, wherein the transceiver transmits the state read signal to the sink device via the serial data line.

An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

In aspects, a Local Interconnect Network (LIN) communication circuit including a first LIN master associated with a first LIN bus and a second LIN master associated with a second LIN bus is disclosed. A data link is connected between the first and second LIN masters. A first mirroring client is established at the first LIN master for receiving message bits corresponding to a LIN message in a first slot on the first LIN bus and for transmitting the message bits bitwise over the data link. A second mirroring client is established at the second LIN master for receiving the message bits and transmitting them over the second LIN bus. The first and second LIN masters include synchronised schedule tables such that the message bits on the second LIN bus are transmitted in a corresponding slot to the first.

One embodiment is directed to a multi-rack rack controller for an automated infrastructure management (AIM) system comprising a plurality of independent patching equipment bus interfaces. Another embodiment is directed to a rack controller comprising at least one rack controller interface configured to connect the rack controller to another rack controller. Each rack controller interface comprises a respective termination circuit. The rack controller is configured to determine whether each rack controller interface is connected to another rack controller as a function of a respective sense signal developed by the termination circuit associated with said rack controller interface. Another embodiment is directed to a rack controller comprising a base unit having a locate button disposed on the front of the base unit. Other embodiments are disclosed.

A Universal Serial Bus (USB) connector functionality modification system includes a USB connector coupled to a first subsystem and a second subsystem by a multiplexer device. A USB connector functionality modification subsystem is coupled to the multiplexer device and operates to receive a USB connector functionality modification instruction while the multiplexer device is configured to allow the first subsystem to transmit and receive data via the USB connector and the second subsystem cannot transmit and receive data via the USB connector. In response to receiving the USB connector functionality modification instruction, the USB connector functionality modification subsystem reconfigures the multiplexer device to allow the second subsystem to transmit and receive data via the USB connector while the first subsystem cannot transmit and receive data via the USB connector.