Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.

Bus system comprising a first bus and a second bus, wherein the first bus is connected to the second bus through a bridge and a multiplexer. A first master has access to the second bus via the first bus, the bridge and the multiplexer. A second master has access to the second bus via the multiplexer. The bridge comprises an arbitration unit which is arranged to allow both a first master and a second master access to the second bus in such a way that no access is disturbed or lost.

In an example in accordance with the present disclosure, a system is described that includes a hub for routing data traffic between a first computing device and a second computing device. A detection device of the system detects a communication protocol between the computing devices. A switch of the system routes traffic directly between the computing devices when a first communication protocol is detected. When a second communication protocol is detected, the switch re-routes traffic of the first type from the first computing device back to the hub to convert the traffic of the first type to a second type and routes converted traffic directly to the second computing device.

A communication system includes a central, zone ECUs capable of communicating with the central ECU via a communication bus, and zone ECUs capable of communicating with the central ECU via a communication bus. The central ECU periodically transmits, to the communication buses, a count signal including a count value counted up every time the count signal is transmitted, transmits a control signal including a start count value and control content to the communication buses, and sets a transmission priority of the count signal to be higher than a transmission priority of the control signal. The zone ECUs receive the count signal and the control signal, after the control signal is received, when the count value included in the received count signal becomes equal to the start count value included in the control signal, an operation corresponding to the control content included in the control signal is started.

Apparatuses and methods for extracting ordered data sub-components from a data item are disclosed. A received data item has a data structure to accommodate multiple data sub-components. The data item indicates which data sub-components are valid. Adders sum respective subsets of indications of the valid data sub-component positions, with each adder covering one more position than the previous adder. Transitions of the counts generated by the respective adders are used to determine the ordinal valid data sub-component positions in the data item, which can then be output on the basis of the data item and the identified transition positions. Without requiring feedback paths from an identified earlier ordinal position to identify a later ordinal position, the set of ordered data sub-components can be extracted more quickly.

The invention relates to an interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. Each stage includes switching elements having input pins and output pins. The input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals. The input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage.

A method may include transferring data from a host to an encryption offload engine through an interconnect fabric, encrypting the data from the host at the encryption offload engine, and transferring the encrypted data from the encryption offload engine to a storage device through a peer-to-peer connection in the interconnect fabric. The method may further include transferring the encrypted data from the storage device to the encryption offload engine through a peer-to-peer connection in the interconnect fabric, decrypting the encrypted data from the storage device at the encryption offload engine, and transferring the decrypted data to the host through the interconnect fabric. The method may further include transferring the encrypted data from the storage device to the host, and verifying the encryption of the encrypted data at the host.

Packet routing within a multi-chip processing system is shown. A first chip has a first interconnect bus, and a first microprocessor coupled to the first interconnect bus. The first interconnect bus has a first routing register. When the first microprocessor operates the first chip as a source node to output a packet to be transferred to a destination node, routing information indicating a routing path from the source node to the destination node is written into the first routing register and then loaded from the first routing register to a header of the packet. While being transferred within the multi-chip processing system from the source node to the destination node, the packet is guided along the routing path indicated in the routing information carried in the header of the packet.

An apparatus comprises interface circuitry to receive requests and selection circuitry responsive to the interface circuitry receiving a given request to select, from a pool of items, at least one selected item to be associated with the given request. The selection circuitry comprises a plurality of nodes arranged in a tree structure, each node being configured to select m output signals from n input signals provided to that node, wherein n>m. The apparatus comprises control circuitry configured to output, in dependence on a type of the given request, a suppression signal, and the tree structure comprises a gate node configured to suppress, in response to the suppression signal having a first value, selection from input signals received from a given portion of the tree structure to prevent a subset of the pool of items from being selected for at least one type of request.

A system includes a printed circuit board (PCB) on which is disposed memory components and a processor disposed on the PCB and coupled between the memory components and a host memory controller. The processor comprises a memory channel network (MCN) memory controller to handle memory requests associated with the memory components; a local buffer; and a core coupled to the MCN memory controller and the local buffer. The core executes an operating system (OS) running a network software layer and a distributed computing framework; and an MCN driver to: receive a network packet from the network software layer; store the network packet in the local buffer; and assert a transmit polling field of the local buffer to signal to the host memory controller that the network packet is available for transmission to a host computing device.