An integrated circuit with an adaptive UART serial interface includes at least one input section through which a signal is input from a user, at least one output section through which information is output in a predetermined form, and a microcontroller unit (MCU), independently of the microcontroller unit (MCU), and communicates with the microcontroller unit to control, on the basis of the input signal generated from the at least one input section, output driving of the output section corresponding thereto, the integrated circuit including: a serial interface that includes an Rx pin for receiving a data signal from the microcontroller unit by forming a signal reception line with respect to the microcontroller unit and a Tx pin for transmitting a data signal to the microcontroller unit by forming a signal transmission line with respect to the microcontroller unit.

In accordance with an embodiment, an electronic device includes a secure element configured to implement a plurality of operating systems; and a near field communication module coupled to the secure element by a volatile memory.

An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.

A computer-implemented method comprises a topological communications configurator (TCC) of a computing system determining a connections-optimized configuration of processors among compute nodes of the system. Processors included in the compute nodes can execute compute workers of an application of the system and can form intranodal segments of an internodal interconnection topology communicatively coupling the intranodal segments. The intranodal segments can be interconnected via an internodal interconnections fabric. The TCC can determine the connections-optimized configuration based on internodal communications costs corresponding to communications routes among the internodal segments via the internodal interconnection fabric. The computing system can comprise the TCC and can comprise a data-parallel computing system.

The present disclosure provides a mechanism for data transfer for a robot using pre-existing network standards (e.g., USB-C, Thunderbolt, CAN-bus, or Ethernet) and for power delivery, both being implemented through direct contact pins on a robot and the corresponding contact pads on a docking station. The robot can be a legged or wheeled ground vehicle, an aerial vehicle such as a drone, an underwater robot, or any other suitable robots. The docking station may include a computing device, to which the robot can transfer data. The contact pins and pads can be arranged to have a rotational symmetry.

In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

An asynchronous first device in communication with an asynchronous second device. The time for the first device to complete a processing cycle is a first device major frame and the first device major frame comprises a first device dedicated processing time slot at the end of the first device major frame. The first device is configured to send a rescheduling signal to the second device when it has completed a first device major frame. The first device is configured, during every first device dedicated processing slot, to: monitor for a rescheduling signal sent from the second device to the first device; and if a rescheduling signal from the second device is received: reschedule the current first device major frame to a rescheduled first device major frame; wherein the end of the rescheduled first device major frame coincides with the time the rescheduling signal from the second device was received.

A multicore apparatus determines fitness of a candidate for a role. The apparatus includes a multicore system processing device, a plurality of parallel multicore graphics processing devices, a network interface device, a storage device, and a system interface bus. The network interface device provides remote connection to the multicore system processing device. The storage device stores training data including positive and negative examples. The positive examples represent candidates who would be invited to an interview, and the negative examples represent candidates who would not be invited to an interview. The positive and negative examples are used by the plurality of parallel multicore graphics processing devices to train a deep learning model, which is used by the multicore system processing device to determine fitness of the candidate for the role while eliminating unwanted bias.

Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.