Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

A nonvolatile memory system is disclosed. The nonvolatile memory system includes a host device and a storage device connected to the host device through a physical cable including a power line and a data line. The storage device includes: a nonvolatile memory; a link controller configured to temporarily deactivate the data line while supplying power from the host device through the power line; and a memory controller including a user verification circuit configured to authenticate a user of the storage device and change a state of the memory controller according to a verification result, a relink trigger circuit configured to control the link controller based on the state change of the memory controller, and a data processing circuit configured to encrypt and decrypt data.

A new approach is proposed to support hardware-based PCIe link up based on post silicon characterization of an electronic device. A non-volatile storage medium of a bootup unit on the electronic device maintains an initialization sequence for the physical layer of a PCIe link, and a non-volatile storage medium allows flexible programming. During operation, the bootup unit reads from the non-volatile storage medium instructions to program/override one or more PCIe physical layer settings and controller registers for the PCIe link based on the post silicon characterization of the electronic device. The bootup unit is limited to access and override only to the one or more physical layer settings and controller registers of the PCIe link. The entire process of reading the initialization sequence and programming the one or more PCIe physical layer settings and the controller registers happens within time limit constraints of the PCIe specification for latency reduction.

An interface device between a plurality of memory devices and a memory controller includes processing circuitry configured to provide a plurality of controller channels for communicating with the memory controller, to provide a plurality of memory channels for communicating with the plurality of memory devices, and to connect each of the plurality of controller channels to at least one of the plurality of memory channels in a first mode and disconnect the plurality of controller channels from the plurality of memory channels in a second mode.

Framework for network bypass is disclosed herein. Exemplary network bypass apparatus may include a relay, a first connection interface connectable to a network device, a second connection interface connectable to a first communication device, and a third connection interface connectable to a second communication device. The network bypass apparatus may further include a housing enclosing the relay and the first, second and third connection interfaces, wherein the relay communicatively couples the first connection interface and the third connection interface while communicatively decoupling the first connection interface and the second connection interface in response to disconnection of power to the relay during a bypass mode.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

Disclosed are a signal transmission method, device and equipment based on drilling equipment, and a medium, the signal transmission is applied to a signal transmission system of the drilling equipment, the signal transmission system includes a master node and a plurality of slave nodes, and the master node communicates with the slave nodes through a 1-wire bus. The signal transmission method includes: sending, by the master node, an instruction signal coupled by a TTL signal and a data request signal to a specified slave node, wherein the data request signal is a critical identifiable signal with the same period as the TTL signal so as to ensure that the system can identify the logic level of the instruction signal and occupy the 1-wire bus in real time; and receiving, by the specified slave node, the instruction signal, decoupling the instruction signal to obtain the data request signal, obtaining a reply signal according to the data request signal, coupling the reply signal with the TTL signal to obtain a feedback signal, and sending the feedback signal to the master node.

A first component of an industrial automation system includes an electrically erasable programmable read-only memory (EEPROM) storing data identifying the first component. The data identifying the first component is read from the EEPROM by a second component to which the first component is communicatively coupled to authenticate the first component. The first component lacks a processor and a microcontroller, and does not run firmware.

This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

Connector receptacles that can provide audible feedback to inform a user that a card has been properly inserted, and can include structures to protect contacts in a connector receptacle from damage due to an improper card insertion. An example can provide a connector receptacle having a click module to provide audible feedback indicating that a card has been fully inserted. Another example can provide a connector receptacle having movable contacts that can remain out of an insertion path until the card is at least partially inserted.