A cable connection information display system includes a cable having a first cable connector, and a first cable connection information display subsystem that is included on the cable adjacent the first cable connector. The first cable connection information display subsystem includes a first display device, and a first connection information receiving subsystem that is coupled to the first cable connector and the first display device. The first connection information receiving subsystem receives first connection information, which identifies at least a first computing device and a first port, via the first cable connector and from the first computing device that includes the first port that is connected to the first cable connector. The first connection information receiving subsystem then provides the first connection information for display on the first display device to identify the first computing device and the first port.

The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash memory card. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: determining whether a temperature of a motherboard has exceeded a threshold through a temperature sensor IC after receiving a host read or write command from a host side; requesting a flash memory card to enter a sleep state when the temperature of the motherboard has exceeded the threshold; and instructing the flash memory card to perform an operation corresponding to the host read or write command when the temperature of the motherboard hasn't exceeded the threshold. The bridge IC and the temperature sensor IC are disposed on the motherboard, the flash memory card is inserted into a card slot on the motherboard, and the bridge IC is coupled to the temperature sensor IC and the flash memory card through a circuit of the motherboard.

Methods and apparatus relating to a scalable address decoding scheme for Compute Express Link™ or CXL™ Type-2 devices with programmable interleave granularity are described. In an embodiment, configurator logic circuitry determines an interleave granularity and an address range size for a plurality of devices coupled to a socket of a processor. A single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor is stored in memory. A memory access transaction directed at a first device from the plurality of devices is routed to the first device in accordance with the SAD rule. Other embodiments are also disclosed and claimed.

A compression attached memory module (CAMM) includes a memory device, a first array of compression contact pads and a second array of compression contact pads. The first array of compression contact pads receives a first memory channel and a second memory channel. The first memory channel is coupled to the first memory device. The second array of compression contact pads is coupled to a subset of the first compression contact pads associated with the second memory channel.

An information handling system includes a printed circuit board, a z-axis compression connector, and a compression attached memory module (CAMM). The compression connector coupled receives a first memory channel and a second memory channel from the PCB. The CAMM receives the first memory channel and the second memory channel from the first compression connector. The CAMM is configured to provide memory transaction on only the first memory channel.

An integrated circuit (IC) device according to an example includes an interconnect bus to communicate with an external memory device, wherein the interconnect bus includes a plurality of different channels to be coupled directly to a first set of masters. The IC device includes a crossbar unit to be coupled to a second set of masters, wherein the crossbar unit is to monitor bandwidth usage at the plurality of different channels, and selectively route traffic between the second set of masters and the plurality of different channels based on the monitored bandwidth usage.

An information handling system includes a first z-axis compression connector having a first depth, a first memory module, a second z-axis compression connector having a second depth that is greater than the first depth, a second memory module, and a printed circuit board. A first side of the first compression connector is affixed to the printed circuit board at a first location and a first surface of a first memory circuit board of the first memory module is affixed to a second side of the first compression connector. A first side of the second compression connector is affixed to the printed circuit board at a second location adjacent to the first location and the first side of a second memory circuit board of the second memory module is affixed to a second side of the second compression connector.

Priority reversing data traffic for latency sensitive peripherals, including receiving a connection notification and parameters of a peripheral; identifying, from the parameters, that an interface type associated with the peripheral is a bulk interface, the bulk interface associated with a first communication channel between the IHS and the peripheral and having a first latency; determining, based on the bulk interface type and a data traffic priority associated with the peripheral, that the data traffic associated with the peripheral is priority-inversed; in response to a communication request by an application executing on the IHS for communication with the peripheral, determining that the data traffic associated with the peripheral is priority-inversed, and in response, placing the data traffic in a queue associated with a second communication channel defined between the IHS and the peripheral, the second communication channel having a second latency, wherein the first latency is greater than the second latency.

A tablet computer is provided, which includes a sensor section operable to detect positional input by a human operator and output a positional input signal; a display, laid over the sensor section, operable to receive and display a video signal; and a processor, coupled to a memory storing programs for running an operating system (OS) and executing software loaded to the memory, the processor being operable to receive and process the positional input signal from the sensor section and to output a video signal of the OS and the software to the display. The tablet computer further includes a sensor signal filter capable of selectively communicating the positional input signal from the sensor section to the processor, to a separate external processor, or to neither the processor nor the separate external processor; and a display switch capable of coupling the display to the processor or to the separate external processor.

A data transmission method stores target data from an initial storage area of an initial platform to an initial temporary storage area of the initial platform in response to a first user operation. The target data is uploaded to a cloud platform. The cloud platform stores the target data. A target platform downloads the target data from the cloud platform to a second designated location of the target platform in response to a second user operation. The initial platform stores the target data from the initial temporary storage area to a third designated location of the initial platform in response to a third user operation. The method improves the efficiency of data transmission between different platforms.