A composite connector is used for receiving a first and a second docking connectors (700, 800) and includes: an insulation main body (1); a first tongue (11) and a second tongue (12), and plural first, second and third terminals (3, 4, 5). The first tongue (11) and the second tongue (12) are connected to the insulation main body (1); the first terminals (3) and the second terminals (4) are disposed on two surfaces of the first tongue (11) for allowing the first docking connected (700) to be connected; the third terminals (5) are disposed on any surface of the second tongue (12) for allowing the second docking connector (800) to be connected. Accordingly, two interfaces can be integrated in the same connector, thereby achieving an objective of composite operation.

The present disclosure discloses an apparatus for read/write operations on a serial attached small computer system interface (SAS) hard disk through a universal serial bus (USB) interface. The apparatus includes: a case, where the case is internally provided with a printed circuit board assembly (PCBA) mainboard, the PCBA mainboard is provided with a controller, a power management module, an SAS to serial advanced technology attachment (SATA) protocol conversion module, an SATA to USB protocol conversion module, a USB interface and an SAS hard disk access interface, and the controller controls the PCBA mainboard to conduct the read/write operations on the SAS hard disk; and other components. The apparatus facilitates rapid read/write operations on the SAS hard disk by a consumer through the USB interface, and also improves heat dissipation efficiency of an apparatus body.

Embodiments are disclosed for a standardized car interface for cockpit controllers in vehicles. In one example, a system for coupling a vehicle cable for communication with components of an infotainment system, comprises: a housing, a domain controller, and a first connector interface including all connections for the domain controller. In the event that a first domain controller is exchanged for a second domain controller, a collection of user preferences may be transferred between the first domain controller to the second domain controller.

According to one embodiment, a memory system is disclosed. The system includes a nonvolatile memory, a controller which controls the nonvolatile memory and to which a first voltage is supplied, and a circuit to which first and second signals from a host device are input, or the first signal is not input and the second signal is input from the host device, when the memory system is connected to the host device. The circuit converts a second voltage of the second signal into the first voltage when the first and second signal have the second voltage and the second voltage is lower than the first voltage, and does not convert a voltage of the second signal into the first voltage when the first signal is not input and the voltage of the second signal is the first voltage.

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

The systems and methods for bus ownership in a system power management interface (SPMI) bus may include two or more masters on the SPMI bus, and bus ownership may be passed between masters. The current owner of the bus is responsible for providing a clock signal on the clock line of the SPMI bus. To avoid problems caused by ringing of the clock signal being sent on a conductor that exceeds the SPMI specification, the original master (from whom bus ownership is being transferred) holds the clock line of the SPMI bus at a logical low for a clock delay value that is based on conductor length.

The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.

A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

A storage array and systems for configuring a storage array are provided. In one example, the storage array includes a motherboard. The motherboard includes a first compute module and an input/output (I/O) mid-plane that is routed to the first compute module. The I/O mid-plane has a plurality of peripheral component interconnect express (PCIe) lanes coupled to the first compute module. A bridge module interconnect is routed to the I/O mid-plane via one or more of the plurality of PCIe lanes of the I/O mid-plane. The bridge module interconnect provides bridge connections to receive to two or more types of protocol bridge modules. A storage mid-plane provides integrated routing between each of a plurality of drive connectors and each of the bridge connections of the two or more types of protocol bridge modules of the bridge module interconnect. In some configurations, the I/O mid-plane is eliminated and that functionality is integrated into a combination of boards referred to as upper and lower storage docking modules, while maintaining the storage mid-plane.

A tablet cover (100) and circuitry (400) provide for convenient connection of a tablet (105) or other personal electronic device to additional memory, functions, and features as provided by an internal device (215) and/or an external device (160). The circuitry selectively connects the tablet, the external device, and the additional memory together. The additional memory is internal to the case and is thereby protected from loss or damage due to accidental impact.