An apparatus is provided. The apparatus comprises interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to determine that a first composite link of a plurality of composite PCIe links terminating at the same PCIe root port lacks support for enabling a desired power saving state or an exit latency for the first composite link is above a first latency threshold. The processing circuitry is further configured to determine whether an exit latency for a second composite link of the plurality of composite PCIe links is below a second latency threshold and selectively trigger at least one sub-link of the second composite link to enable the desired power saving state if the exit latency for the second composite link is below the second latency threshold.

In one embodiment, an apparatus couples to a host processor over a Compute Express Link (CXL)-based link. The apparatus includes a transaction queue to queue memory transactions to be completed in an addressable memory coupled to the apparatus, a transaction cache, conflict detection circuitry to determine whether a conflict exists between memory transactions, and transaction execution circuitry. The transaction execution circuitry may access a transaction from the transaction queue, the transaction to implement one or more memory operations in the memory, store data from the memory to be accessed by the transaction operations in the transaction cache, execute operations of the transaction, including modifying data from the memory location stored in the transaction cache, and based on completion of the transaction, cause the modified data from the transaction cache to be stored in the memory.

A power supply device including a register circuit, an internal control circuit, and a storage circuit is disclosed. The register circuit includes a first sub-register circuit and a second sub-register circuit. The first sub-register circuit and the second sub-register circuit are configured to take turns to temporarily store a data transmitted form an external control circuit. The internal control circuit is coupled to the register circuit, and the internal control circuit is configured to obtain the data temporarily stored in the first sub-register circuit and the second sub-register circuit. The storage circuit is coupled to the internal control circuit, and the storage circuit is configured to obtain the data from the internal control circuit and to store the data.

Systems, methods and computer software are disclosed for fronthaul. In one embodiment a method is disclosed, comprising: providing a virtual Radio Access Network (vRAN) having a centralized unit (CU) and a distributed unit (DU); and interconnecting the CU and DU over an Input/Output (I/O) bus using Peripheral Component Interconnect-Express (PCIe); wherein the CU and the DU include a PCI to optical converter and an optical to PCI converter.

Presently disclosed are systems and methods for generating customized filtered-and-partitioned market-data feeds. In an embodiment, an output-feed profile is maintained in data storage at a market-data-processing device (MDPD). The output-feed profile specifies a subset of ticker symbols and a ticker-symbol-based feed-partitioning scheme. An input feed of order-book updates to ticker symbols is received at the MDPD from an upstream device. At the MDPD, a customized market-data output feed is generated according to the maintained output-feed profile at least in part by filtering the input feed down to the order-book updates to ticker symbols in the specified subset and partitioning the filtered feed according to the specified ticker-symbol-based feed-partitioning scheme. The customized market-data output feed is transmitted from the MDPD to a downstream device.

A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

Disclosed are various embodiments for various approaches for implementing trust domains to provide boundaries between PCIe devices connected to the same PCIe switch. A first trust identifier can be assigned to a first virtual machine hosted by the computing device. The first trust identifier can also be assigned to a first PCIe device assigned to the first virtual machine. Later, it can be determined that a second PCIe device connected to the PCIe switch is assigned a second trust identifier assigned to a second virtual machine. An Address Control Services (ACS) direct translated bit for peer-to-peer memory requests in the PCIe switch can be disabled in response to a determination that the second PCIe device is associated with the second trust identifier assigned to the second virtual machine.

A PCIe resource management system includes a PCIe resource registration subsystem and a PCIe resource monitoring subsystem. Assets register to use PCIe resources of other assets and to allow other assets to use their PCIe resources. Assets specify which types of PCIe resources it can borrow, when it can borrow those PCIe resources, and a logical group of other assets from which the asset can borrow the PCIe resources. Assets also specify which types of PCIe resources it will lend, when it will lend those PCIe resources, and a logical group of other assets to which the asset will lend the PCIe resources. The PCIe resource registration subsystem maintains a PCIe resource registration datastore maintaining PCIe borrow and lending rules associated with assets in logical groups of assets. PCIe resources are shared between assets in the logical groups as needed, as determined by the PCIe resource monitoring subsystem.

An electronics assembly including a plurality of midplanes positioned between and coupled to a plurality of electronic components at one side of the plurality of midplanes and at least one electronic component at an opposite side of the plurality of midplanes in a manner so that the midplanes are vertically oriented in parallel relative to each other so as to define spaces therebetween. The midplanes each include electrical traces configured to send signals among and between the plurality of electronic components at the one side of the midplanes and the at least one electronic component at the opposite side of the midplanes.

A host computing device includes a host processor, host memory in electronic communication with the host processor, and an auxiliary service controller. The host computing device also includes a communication interface and a messaging interface between the host processor and the auxiliary service controller. A message handler is stored in the host memory. The message handler is executable by the host processor in response to detecting a messaging interface signal on the messaging interface. Execution of the message handler by the host processor causes a firmware update patch to be read from a shared memory region in the auxiliary service controller via the communication interface.