An enhanced general input/output communication architecture, protocol and related methods are presented.

A communication device is included in a daisy chain connection. A receiver receives a first signal from a preceding device in the daisy chain connection. A transmitter transmits the first signal received in the receiver to a succeeding device in the daisy chain connection. An acceptor accepts a second signal starting from the communication device. The transmitter transmits the second signal accepted in the acceptor to the succeeding device at a transmission rate higher than a transmission rate of the first signal received in the receiver.

Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

A finite state machine is provided that both serializes virtual GPIO signals and messaging signals and that deserializer virtual GPIO signals and the messaging signals. The finite state machine frames the serialized virtual GPIO signals and messaging signals into frames each demarcated by a start bit and an end bit.

An enhanced general input/output communication architecture, protocol and related methods are presented.

An embodiment of the present invention relates to physical interfaces, especially those used on consumer electronics devices. A processor, in which an embodiment of the disclosed invention is deployed, includes a physical interface for connecting to and communicating with a peripheral device, the peripheral device being configured to operate according to a standard communications protocol or to a different protocol which is adapted to have a more bandwidth-efficient performance. The processor detects which of the two protocols the attached peripheral device uses and configures the physical interface to operate according to the detected protocol. An embodiment of the invention allows for new, bandwidth-efficient communications protocols to be executed across existing standardized physical interface hardware, thereby allowing for easier acceptance of the new protocols within the consumer electronics industry. Bandwidth-efficient communications protocols advantageously allow for more convenient transfer of media content or for big-data applications to be more conveniently handled.

A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a flow control signal over a link of an interconnect, the flow control signal indicating flow control credits allocated for the device on the channel. The flow control logic is further to update the value of flow control credits based on activity of the device on the channel.

An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a command signal and creates data transmission link to the computer device. The master storage unit has at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to transmit the command signal from the master storage unit to the slave storage unit.