Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

A storage device includes a host interface configured to communicate with a host device according to a first protocol through an input terminal, an output terminal, and a clock terminal. The input terminal is configured to receive an input signal from the host device according to the first protocol. The output terminal is configured to output an output signal to the host device according to the first protocol. The clock terminal configured to receive a clock signal from the host device according to the first protocol. The host interface is configured to communicate with the host device according to a second protocol through the clock terminal, the second protocol being different from the first protocol.

A signal processing circuit includes: a plurality of daisy chain-connected AD converters each including a data ready output terminal, a synchronizing signal input terminal, and a serial clock input terminal; a calculator connected to the data ready output terminal of any of the AD converters and for outputting a serial clock to the serial clock input terminal of each of the AD converters when a data ready signal is input; and a reset processor included in the calculator and for outputting a synchronizing signal to the synchronizing signal input terminal of each of the AD converters when an output time lag among data ready signals from each of the AD converters is detected for a predetermined number of times.

A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation. Several fringe timing points are sampled, whereby several of the plurality of fringe timing points are associated with each of the transition edges of the second stream of data bits input to the data interface circuit. The drift amount is compared with a drift correction threshold value and the first optimal sampling point is shifted in time by the drift amount to revise the first optimal sampling point.

A method of transferring control data between a master device and a slave device over a path including at least one intermediate device, such that the path includes multiple path segments between successive pairs of devices. Data is transferred on each path segment in a plurality of frames of data, wherein the frames are synchronized between said path segments. The control data is transmitted in command slots of each frame, wherein a command slot comprises a set of control data bit slots, and wherein a control data bit slot is a time window associated with the transfer of a single control data bit over a single path segment between the devices on the path segment. The control data bit slots for each command slot are subdivided into: a first set of bit slots reserved for the transfer of control data in the direction from the master device to the slave device, and a second set of bit slots reserved for the transfer of control data either in the direction from the master device to the slave device or in the direction from the slave device to the master device. The time positions of the command slots on each path segment are offset from the positions of the command slots on each respective adjacent path segment by at least one control data bit slot.

In some examples, a management controller is to dynamically vary a parameter that controls an operational characteristic of a bus when transferring different portions of information from a memory over the bus during a process of an electronic device in which a cryptographic operation is performed. The different portions of the information from the memory are to be transferred over the bus with different operational characteristics of the bus.

In some aspects, an audio processor may provide, to each digital sample rate converters in a time division multiplexing (TDM) data chain, a set of TDM clocks that include a sample rate clock input and a bit clock input. The digital sample rate converters in each TDM data chain may connect to respective audio ports that each correspond to a stereo channel. The digital sample rate converters in each TDM data chain may receive digital audio inputs via the audio ports. The audio processor may receive, at one or more TDM inputs, a TDM audio stream from each of the one or more TDM data chains, wherein the TDM audio stream mixes the digital audio inputs based on the sample rate clock input and the bit clock input. Numerous other aspects are described.

Z-dimension cache layer pipelining is described. In one or more implementations, a device includes a stacked cache having a plurality of cache layers communicatively pipelined by an interconnect that outputs responses from the cache layers for processing during a common clock cycle. In one or more implementations, a system includes a stacked cache having a plurality of cache layers, with each cache layer implemented on a different respective die within a stack of dies, a cache controller configured to send requests to the cache layers and process responses received from the cache layers, and an interconnect configured to synchronize communication between the cache controller and the stacked cache by pipelining the responses to arrive at the cache controller during a common clock cycle.

A bus configuration system includes a plurality of driver integrated circuits (ICs) coupled sequentially on a daisy chain, and a bus controller coupled to the plurality of driver ICs. Each driver IC includes a plurality of ports. The bus controller is used to generate a port definition code for configuring each port of the each driver IC. The bus controller includes a clock output port used to output a clock signal and a data output port used to output a data signal. When a port of the plurality of ports detects the clock signal, the port is configured as a clock input port.