An apparatus includes a plurality of output ports and a processor. The output ports may each be configured to connect to a respective trigger device and generate an output signal to activate the respective trigger device. The processor may be configured to determine a number of the trigger devices connected to the output ports, determine a timing between each of the number of the trigger devices connected, convert the timing for each of the trigger devices to fit a standard timing using offset values specific to each of the trigger devices and perform a trigger routine to trigger the output signal for each of the trigger devices connected. The trigger routine may activate each of the trigger devices connected according to an event. The offset values may delay triggering the trigger devices to ensure that the trigger devices are sequentially activated at intervals that correspond consistently with the standard timing.

A method for executing an application in a multitasking system is provided. The application is composed of at least one task for which the temporal triggering is specified in a first temporal reference frame that is asynchronous relative to the physical time, called first external clock domain, defined by a synchronous basic clock with changes of state of a peripheral device of the system. The method comprises a set of steps executed by the system upon reception of an occurrence of an interrupt in order to render the execution of the task deterministic or quasi-deterministic.

Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

In an example embodiment, a power switching circuit of an automobile audio bus (A.sup.2B) chip is provided in a bi-directional, multi-node two-wire conductor system that includes a plurality of A.sup.2B chips interconnected on a twisted wire pair bus (A.sup.2B bus), with at least one A.sup.2B chip functioning as a master and the remaining A.sup.2B chips functioning as slaves. The power switching circuit of the A.sup.2B chip powers up a next downstream A.sup.2B chip in the A.sup.2B bus sequentially according to a power switching procedure, and the power switching circuit is configured to detect faults in the A.sup.2B bus before, during, and after the power switching procedure. Each A.sup.2B chip enables power to the next downstream A.sup.2B chip without risk of damage to any components in the system due to line faults on the downstream A.sup.2B bus, or collapse of the power supply at the local A.sup.2B chip.

An apparatus includes a plurality of output ports and a processor. The output ports may each be configured to connect to a respective trigger device and generate an output signal to activate the respective trigger device. The processor may be configured to determine a number of the trigger devices connected to the output ports, determine a timing between each of the number of the trigger devices connected, convert the timing for each of the trigger devices to fit a standard timing using offset values specific to each of the trigger devices and perform a trigger routine to trigger the output signal for each of the trigger devices connected. The trigger routine may activate each of the trigger devices connected according to an event. The offset values may delay triggering the trigger devices to ensure that the trigger devices are sequentially activated at intervals that correspond consistently with the standard timing.

Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

An apparatus includes a plurality of output ports and a processor. The output ports may each be configured to connect to a respective trigger device and generate an output signal to activate the respective trigger device. The processor may be configured to determine a number of the trigger devices connected to the output ports, determine a timing between each of the number of the trigger devices connected, convert the timing for each of the trigger devices to fit a standard timing using offset values specific to each of the trigger devices and perform a trigger routine to trigger the output signal for each of the trigger devices connected. The trigger routine may activate each of the trigger devices connected according to an event. The offset values may delay triggering the trigger devices to ensure that the trigger devices are sequentially activated at intervals that correspond consistently with the standard timing.

Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.