A computer-implemented method, a computer program product, and a computer system for seamless I/O in Fibre Channel point to point topology while a target (or storage) port is changed. The target returns a first World Wide Port Name for a first target port to a pool of World Wide Port Names for ports on the target, in response to detecting that a Fibre Channel link between an initiator port and the first target port is down. The target detects a connection between the initiator port and a second target port. The target determines whether the initiator port issues a request of an initiator initiated Fabric login for connecting to the second target port. In response to determining that the request is issued, the target performs the initiator initiated Fabric login. In response to determining that the request is not issued, the target performs a target initiated Fabric login.

A device for securing USB or Firewire port interconnections includes a microcontroller comprising a processor; a first connector/lead in communication with the microcontroller and configured to be coupled with a USB or Firewire external device; and a second connector/lead in communication with the microcontroller and configured to be coupled with a protected host. An optional user interface communicates with the microcontroller. When the microcontroller detects that the external device is coupled to the first connector/lead, the processor is configured to display a prompt on the user interface for a user to initiate inputs prior to the external device being allowed to connect with the protected host; or is configured to automatically prevent the external device from being connected with the protected host if the external device is on a blacklist of devices known to have device handlers in the protected host at a BIOS level, without modifying the protected host.

Aspects include providing automatic access control and security for a synchronous input/output (I/O) link. Providing automatic access control and security includes initializing devices of a storage environment over a first link to verify that the devices are available within the storage environment; building a table of identifiers, where each of the identifiers is assigned one of the devices that have been initialized; and verifying a first device attempting to perform synchronous I/O commands across the synchronization I/O link by confirming that an identifier assigned to the first device is within the table of identifiers.

The disclosure relates to a light module and the matching housing for a bus node. The light module is provided to be used in a data bus system for transmitting data for light-emitting components via a differential two-wire data bus. The data bus transmits data between a bus master and at least two bus nodes. The data bus is divided by the bus nodes into at least two two-wire data bus sections. The housing comprises at least two rows of connections arranged opposite each other. Each row comprises one negative supply voltage connection and one positive supply voltage connection, which are arranged to be connected in pairs without intersection. The two connections for each of the respective two-wire data bus sections are arranged between the connections for the supply voltages in each row. A light-emitting component is arranged in a recess of the housing.

Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Various examples described herein provide for a management controller that includes a virtual universal serial bus (USB) host controller that can emulate an actual USB host controller to a central processor. A particular endpoint from a number of endpoints is associated with a virtual USB device that is coupled to the virtual USB host controller. The particular endpoint is to refer to a location in a management memory.

Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.

A simplified host accesses SATA and SAS storage media devices by abstracting the SATA and SAS protocols with one full duplex protocol that supports full command queuing to each storage media device, whether SATA or SAS, where the abstraction protocol is performance-centric and supports common high-level read and write access to a pool of storage media devices, each of which may have a SATA or SAS interface. The abstraction protocol is link-agnostic and may be carried via a multiplicity of direct attach or networked interfaces, including but not limited to PCIe, Ethernet (e.g., 1 GbE, 10 GbE, 40 GbE, or 100 GbE), Infiniband, ThunderBolt, Firewire, USB, and/or custom interfaces.