System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A configurable clock tree includes a delay matrix that may be configured such that each the timing of clocks for each of a plurality of data lanes can be optimized for minimum skew. Selections between different versions of a base clock signal and different paths available to the selected version may provide a root clock used for transmitting data on a communications link. The versions of the one or more clock signals may include three versions of a first clock signal. Each version of the first clock signal may be subject to a different delay with respect to the clock signal.

Variable rate display interfaces are disclosed. In an exemplary aspect, a high-speed reverse data transfer is enabled over plural lanes of a display serial interface (DSI) bus during blanking periods. Further increases in bandwidth of each high-speed reverse data transfer may be achieved by increasing DSI clock speed during the blanking periods. Since a display relies on a host clock to send reverse data, the frequency of the reverse data is increased, which effectively increases the bandwidth of reverse channel lanes. By increasing the reverse bandwidth over existing pins in the DSI bus, more data may be transferred to the host, including raw touch/stylus data rather than processed data. The raw data may then be processed by the host's relatively powerful processors. By shifting the processing to the host, the need for a powerful touch screen controller (TSC) and/or a powerful touch display driver integrated circuit (TDDI) may be avoided.

An information handling system includes a first managed system including a first processor and a first management controller and a second managed system including a second processor and a second management controller. The first management controller is coupled to directly communicate with the second management controller. In an embodiment, the first management controller is coupled to the second management controller via a first I2C interface.

A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

A method for data transmission control of inter field programmable gate array (FPGA) and an associated apparatus are provided. The method includes: utilizing a first register device to latch a set of data from a first FPGA according to a first clock, wherein the set of data is arranged and divided into multiple sets of partial data according to attributes of payloads and pointers; utilizing a time-division multiplexing (TDM) interface to transmit the multiple sets of partial data from the first register device to a second register device according to a TDM clock at multiple time points, respectively; and utilizing the second register device to sequentially receive the multiple sets of partial data, in order to output the set of data to a second FPGA, wherein the second FPGA operates according to a second clock different from the first clock.

Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.

A virtual GPIO architecture for an integrated circuit is provided that both serializesvirtual GPIO signals and deserializes virtual GPIO signals without the need for an external clock.

A MIPI D-PHY circuit comprises a main control module, a controlled module, an internal data source generating module, and a configuration register. The main control module and the controlled module are respectively connected to the configuration register, and the main control module is connected to the internal data source generating module. The main control module and the controlled module comprise a clock channel and a data channel respectively. The clock channel and the data channel in the main control module and the data channel and the clock channel in the controlled module both comprise an error detection unit. The MIPI D-PHY circuit provided by the present disclosure adopts the error detection unit to detect the signals of the main control module and the controlled module.

The present invention relates to a 5th-generation (5G) or pre-5G communication system to be provided in order to support a higher data transmission rate than a beyond 4th-generation (4G) communication system such as long term evolution (LTE). The present invention relates to a signal transmission method of a radio frequency (RF) processing device, the method comprising the steps of: generating a pulse signal including a control signal and a clock signal for obtaining synchronization with another RF processing device, which is connected through an interface; and transmitting, to the another RF processing device, at least one from among the pulse signal, a RF signal for communication with a base station, and a power signal for supplying power to the another RF processing device, wherein the clock signal and the control signal are assigned to different time units, and the pulse signal, the RF signal and the power signal are signals of different frequency bands.