Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.

A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to semiconductor interconnects, such as on-package die-to-die (D2D) interconnects, for example. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

The present disclosure provides for calibrating clock signals in an unmatched data input system. In various embodiments, an unmatched data input system uses multi-delay circuits to calibrate a clock signal distributed to various input/outputs in the unmatched data input system. These multi-delay circuits can include coarse delay circuits and fine delay circuits that provide a broad range as well as accurate delay capabilities. Through the use of these multi-delay circuits, the unmatched data input system can optimally align a clock signal with its associated data signal across multiple input/outputs.

One embodiment relates to a method of communicating a data packet stream in which data is re-packed to reduce wasted bandwidth. Data bytes of the data packet stream are received from a first data path and mapped to a second data path that is divided into a plurality of data segments. At least one data byte is mapped to each data segment until an end of, or pause in, the data packet stream. Another embodiment relates to a method of communicating data packets from multiple channels. Multiple data packet flows, each flow corresponding to a channel, is received on a first data path. The data bytes from the first data path are mapped to a second data path that is divided into multiple data segments. At least one data byte is mapped to each data segment until an end of, or pause in, the multiple data packet flows. Other embodiments, aspects, and features of the invention are also disclosed.

Asymmetric power states on a communication link are disclosed. In one aspect, the communication link is a Peripheral Component Interconnect (PCI) express (PCIe) link. PCIe is a point-to-point communication link between two termini. Exemplary aspects of the present disclosure allow the two termini to be in different power states. By allowing the two termini to be in the different power states, an individual terminus may be put into a low-power state even though the other terminus is maintained at a higher-power state. The different power states are enabled by providing switches between a reference clock and respective termini such that the reference clock may selectively be provided to only one terminus of the communication link, allowing that terminus to remain in the higher-power state while the other terminus enters a low-power state that does not require the reference clock.

This disclosure concerns an apparatus of multiple processors, such as microprocessors and communications therebetween and enables efficient half-duplex two-way communication between two processors, each having two logic output pins and two logic input pins, e.g. GPIO pins, available for the communication. For each of the first and the second processor (101, 102), the first logic output pin (11, 21) is connected to the second logic input pin (14, 24) of the respective other processor (101, 102), and for each of the first and the second processor (101, 102), the second logic output pin (12, 22) is connected to the first logic input pin (13, 23) of the respective other processor (101, 102). Each of the first and the second processor (101, 102) is operable in a transmit mode by controlling the second logic output pin (12, 22) and in a receive mode by determining a sequence of data bits (D7-D0) from the logic data signal (DAT) received on the first logic input pin (13, 23) in response to state transitions of the logic clock signal (CLK) received on the second logic input pin (14, 24).

Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.