The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T.sub.1 . . . T.sub.4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T.sub.1 . . . T.sub.4 at least one of the four signals has an edge to enable clock recovery at the second IC.

A transceiver device includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload to generate a first payload in the second mode, and transmits a clock training pattern and the first payload through the first line and the second line. The receiver decodes the first payload and outputs reception data corresponding to the original payload in the second mode.

In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.

Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

Provided are a storage device configured to perform high-speed link startup and a storage system including the storage device. The storage system performs data communication through a connected transmission lane and a connected reception lane from among a plurality of lanes between a host and the storage device. The host transmits an activate period of the connected transmission lane, which is less than a first time period, to the connected reception lane, and the storage device receives the activate period of the connected reception lane, which is less than the first time period. The host and the storage device perform link startup in a high-speed mode through the connected transmission lane and the connected reception lane, based on the activate period being less than the first time period.

In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.

A slave device for IO-Link communication with a master device, wherein the master device and the slave device operate on a common basic timing, the slave device including at least one Universal Asynchronous Receiver Transmitter (UART) module configured to detect an INIT request sent from the master device during communication setup, calculate an actual timing of the master device from the INIT request and correct an initial timing of the slave device to an actual timing of the slave device based on the actual timing of the master device.

Communication devices and systems with correct regeneration of an audio signal are disclosed. In one example, a communication device measures a number of predetermined reference clocks included in one cycle of a frequency divided signal, on the basis of an audio master clock having a frequency obtained by multiplying a frequency of a sampling clock to sample an audio signal, a frequency division ratio of a frequency divided signal of the audio master clock, and a predetermined reference clock. A packet generator generates a packet including information including the measured number, a bit width of serial data (SD) conforming to an Inter-IC Sound (I2S) standard, the frequency of the sampling clock, a frequency division ratio of the frequency divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD.

Provided are a storage device configured to perform high-speed link startup and a storage system including the storage device. The storage system performs data communication through a connected transmission lane and a connected reception lane from among a plurality of lanes between a host and the storage device. The host transmits an activate period of the connected transmission lane, which is less than a first time period, to the connected reception lane, and the storage device receives the activate period of the connected reception lane, which is less than the first time period. The host and the storage device perform link startup in a high-speed mode through the connected transmission lane and the connected reception lane, based on the activate period being less than the first time period.

An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing a link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is permitted, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and subsequently operates the communication link using the enhanced speed.