The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T.sub.1 . . . T.sub.4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T.sub.1 . . . T.sub.4 at least one of the four signals has an edge to enable clock recovery at the second IC.

A device may include an input for receiving information communicated from a host to the device and a controller configured to recover a device reference clock on the device, the device reference clock proportional to a host reference clock of the host, when clock signaling from the host to the device is unavailable. The controller may recover the device reference clock by measuring a ratio between the host reference clock and the device reference clock of the device by monitoring, with the device, host start-of-frame markers communicated from the host to the device via the input, creating a recovered reference clock based on the measured ratio, and creating local start-of-frame markers that are phase locked with the host start-of-frame markers based on the recovered reference clock.

A data transmission device includes an embedded clock-scheme differential signal transmission circuit and an in-phase signal transmission circuit. The data transmission device accepts transmission-object data and a transmission instruction for the data. Then, the data transmission device determines between the embedded clock-scheme differential signal transmission circuit and the in-phase signal transmission circuit, by which circuit to transmit the data, based on at least either one of the data and the transmission instruction. The data transmission device causes the determined circuit to transmit the data.

Technology for an electronic circuit is described. The electronic circuit can include one or more timed general-purpose input/output (GPIO) pins and a controller. The controller can receive touch sensor data pulses from a plurality of touch sensor integrated circuits (ICs) that are each communicatively coupled to the electronic circuit. A first touch sensor data pulse received from a first touch sensor IC in the plurality of touch sensor ICs can be time synchronized with a second touch sensor data pulse received from a second touch sensor IC in the plurality of touch sensor ICs using the one or more timed GPIO pins. The controller can combine the touch sensor data pulses received time synchronously from each of the plurality of touch sensor ICs to produce joint touch sensor data. The controller can perform joint processing of the joint touch sensor data.

A method for a Mobile Industry Processor Interface (MIPI) master device for improving clock recovery at a MIPI slave device includes: transmitting a symbol sequence including a plurality of consecutive symbols which include at least one of a first symbol value and a second symbol value to the MIPI slave device prior to transmitting packet data to the MIPI slave device, wherein the first symbol value and the second symbol value bring relatively larger encoding jitters than other symbol values.

Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing a link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is permitted, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and subsequently operates the communication link using the enhanced speed.

In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.

A method and system for maximizing bandwidth of a Peripheral Component Interconnect Express (PCIe) Peer-to-Peer (P2P) connection determine a maximum bandwidth and a maximum read request size of a first device, determining a maximum bandwidth and a minimum payload size of a second device, calculate a calculated maximum payload size of the second device by using the maximum read request size of the first device and a bandwidth ratio between the first device and the second device, compare the minimum payload size of the second device with the calculated maximum payload size, and set an operational payload size of the second device to the calculated maximum payload size when the calculated maximum payload size is equal to or greater than the minimum payload size.

A frequency calibration method applied to a Universal Serial Bus (USB) device includes: coupling the USB device to a USB host, wherein the USB device comprises at least a programmable oscillator; utilizing the USB device to extract a low frequency periodic signal from the USB host; calibrating the programmable oscillator of the USB device according to the low frequency periodic signal, to make the programmable oscillator generate an oscillating signal having a predetermined frequency; and when the USB device receives the low frequency periodic signal from the USB host, controlling the USB device to generate a predetermined signal having a frequency higher than a frequency of the low frequency periodic signal to the USB host, to make the USB host continuously generate the low frequency periodic signal to the USB device.