Embodiments discussed herein refer to systems, methods, and circuits for conforming to power up sequencing rules of a conventional hard-wired data connection even though the hard-wired data connection that would ordinarily exist between two data controllers has been replaced with one or more contactless connectors. A consequence of replacing the hard-wired connection with a contactless connector is that the data controllers no longer directly control the power sequencing between the controllers because they are not able to directly communicate with each other over the hard-wired data connections. Power sequence assist circuitry may be used to assists the data controllers in establishing a link in accordance with the power sequencing rules of a particular wired interface despite the intentionally broken hard-wired data connection between the two controllers by instructing the contactless connectors to communicate with their respective data controllers in compliance with the power sequencing rules.

The present invention provides a scheduling method for a peripheral component interconnect express (PCIe) switch of an electronic system. The PCIe switch is utilized for handling input/output requests of a host of the electronic system. The scheduling method includes the PCIe switch determining a scheduling sequence of message signal interrupts (MSIs) and read/write requests corresponding to the input/output requests according to amount of the message signal interrupts corresponding to the input/output requests; and the PCIe switch handling the message signal interrupts and the read/write requests according to the scheduling sequence.

Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

Techniques and systems for performing calibration. A method includes: creating a common calibration pool for performing a calibration operation for two or more communication links, wherein the calibration operation is common to the two or more communication links; and performing a calibration on each of the two or more communication links using the common calibration pool by receiving a calibration request associated with the common calibration operation via a link calibration interface, wherein the calibration request is from at least one of the two or more communication links, upon determining the calibration agent is available to handle the calibration request, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, and performing the common calibration based on the retrieving.

The present disclosure relates to a circuit for calibrating a baud rate. The circuit includes: a first counter connected to a receiving module of a serial port chip and configured to record a first low level duration of a data frame received by the receiving module; a second counter configured to: receive a bit sampling pulse generated from sampling the data frame according to a current baud rate of the receiving module, and record a quantity of the bit sampling pulse in the first low level duration; a divider, connected to the first counter and the second counter and calculate a calibration baud rate according to the first low level duration and the quantity of the bit sampling pulse in the first low level duration; and a selector, connected to the receiving module and the divider and configured to output the calibration baud rate to the receiving module.

Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

Techniques and systems for performing calibration. A method includes: creating a common calibration pool for performing a calibration operation for two or more communication links, wherein the calibration operation is common to the two or more communication links; and performing a calibration on each of the two or more communication links using the common calibration pool by receiving a calibration request associated with the common calibration operation via a link calibration interface, wherein the calibration request is from at least one of the two or more communication links, upon determining the calibration agent is available to handle the calibration request, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, and performing the common calibration based on the retrieving.

In an information processing device serving as a PCIe system including a host device and a plurality of memory devices, one of the plurality of memory devices is defined as a master memory. The other memory devices are defined as slave memories, and are logically coupled to the master memory. The plurality of memory devices thus constitute a single virtual storage. When accessing is performed from a root complex to the plurality of memory devices constituting the single virtual storage, the root complex hands over a bus master to the master memory. The master memory receives a command regarding the accessing from the root complex, changes address information used for the accessing in the command regarding the accessing, based on a logical relationship with the slave memories, and sends changed command regarding the accessing to the slave memories.

Systems, apparatuses, and methods for performing transmit equalization at a target high speed are disclosed. A computing system includes at least a transmitter, receiver, and a communication channel connecting the transmitter and the receiver. The communication channel includes a plurality of lanes which are subdivided into a first subset of lanes and a second subset of lanes. During equalization training, the first subset of lanes operate at a first speed while the second subset of lanes operate at a second speed. The first speed is the desired target speed for operating the communication link while the second speed is a relatively low speed capable of reliably carrying data over a given lane prior to equalization training. The first subset of lanes are trained at the first speed while feedback is conveyed from the receiver to the transmitter using the second subset of lanes operating at the second speed.

Disclosed embodiments include a network switch having a first group of switch elements and a second group of switch elements. The second group of switch elements is cross-connected to the first group of switch elements to passively route network traffic through the network switch in accordance with a predefined configuration.