Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.

A method, system, and apparatus for setting an on-chip password is provided. In an embodiment, a method for programming an on-chip password includes determining a desired logic state for a field-effect transistor according to the on-chip password. The desired logic state is one of a first logic state and a second logic state. The method also includes subjecting one of a source and a drain of the field-effect transistor to hot-carrier stress according to the desired logic state to produce one of a symmetric state of the field-effect transistor and an asymmetric state of the field-effect transistor. The symmetric state corresponds to one of the first and second logic states. The asymmetric state corresponds to the other one of the first and second logic states.

A microcontroller includes two processing blocks that respectively have a Central Processing Unit (CPU) and a peripheral circuit, where an access to the peripheral circuit in each of the processing blocks, that is, to a Read-Only Memory (ROM) or a Pulse Width Modulator (PWM) signal generator, is limited only from the CPU disposed in the same processing block. Thereby a fail-safe functionality of the microcontroller is improved.

A microcontroller includes distinct electronic functions and an interconnection circuit capable of transmitting in wireless fashion data between the functions. The microcontroller can be operated by writing configuration characteristics into a memory of the interconnection circuit for electronic functional circuits that do not have configuration characteristics contained in the memory and erasing configuration characteristics from the memory for electronic functional circuits that have configuration characteristics contained in the memory but are determined to not be able to wirelessly communicate with the interconnection circuit. Data can be wirelessly transmitted between the interconnection circuit and electronic functional circuits having configuration characteristics contained in the memory.

Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

A method, system, and apparatus for setting an on-chip password is provided. In an embodiment, a method for programming an on-chip password includes determining a desired logic state for a field-effect transistor according to the on-chip password. The desired logic state is one of a first logic state and a second logic state. The method also includes subjecting one of a source and a drain of the field-effect transistor to hot-carrier stress according to the desired logic state to produce one of a symmetric state of the field-effect transistor and an asymmetric state of the field-effect transistor. The symmetric state corresponds to one of the first and second logic states. The asymmetric state corresponds to the other one of the first and second logic states.

The present disclosure provides a data read-write scheduler and a reservation station for vector operations. The data read-write scheduler suspends the instruction execution by providing a read instruction cache module and a write instruction cache module and detecting conflict instructions based on the two modules. After the time is satisfied, instructions are re-executed, thereby solving the read-after-write conflict and the write-after-read conflict between instructions and guaranteeing that correct data are provided to a vector operations component. Therefore, the subject disclosure has more values for promotion and application.

A controller for a vehicle includes a main control unit, at least one first secondary control unit, and a switching device. The main control unit is configured to execute processes of critical or safety-related applications. The at least one first secondary control unit is configured execute agile applications. The switching device is configured to deactivate the at least one secondary control unit. The main control unit is also configured, in the event of the occurrence of a predefined safety-related event, to deactivate the at least one secondary control unit by means of the switching device.

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

The present disclosure provides a data read-write scheduler and a reservation station for vector operations. The data read-write scheduler suspends the instruction execution by providing a read instruction cache module and a write instruction cache module and detecting conflict instructions based on the two modules. After the time is satisfied, instructions are re-executed, thereby solving the read-after-write conflict and the write-after-read conflict between instructions and guaranteeing that correct data are provided to a vector operations component. Therefore, the subject disclosure has more values for promotion and application.