A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

A processor including a memory controller for interfacing an external memory and a programmable functional unit (PFU). The PFU is programmed by a PFU program to modify operation of the memory controller, in which the PFU includes programmable logic elements and programmable interconnectors. For example, the PFU is programmed by the PFU program to add a function or otherwise to modify an existing function of the memory controller enhance its functionality during operation of the processor. In this manner, the functionality and/or operation of the memory controller is not fixed once the processor is manufactured, but instead the memory controller may be modified after manufacture to improve efficiency and/or enhance performance of the processor, such as when executing a corresponding process.

An information processing apparatus comprises: a programmable circuit unit comprising a partial reconfiguration unit; a storage unit used by each of logic circuits configured in the partial reconfiguration unit; and a control unit that controls a logic circuit that becomes an access destination, in accordance with receiving an access command, wherein the control unit compares an address space indicating the access destination of the access command with the signal that is output from the partial reconfiguration unit due to the partial reconfiguration unit being configured using circuit information included in the configuration data, and controls to set as an access destination the logic circuit configured in the partial reconfiguration unit outputting the signal matching the address space indicating the access destination of the access command.

A programming file including a first module is loaded to a programmable component. And then, the programmable component is dis-reset. Subsequently, first data is loaded to a memory connecting with the programmable component, to enable the first module in the programmable component to convert the first data of the memory into second data. After the first module of the programmable component converts the first data of the memory into the second data, a second module is loaded to the programmable component. The first module in the programming file is then replaced with the second module, to enable the second module to access the second data.

A system on chip (SoC) module is described herein, wherein the SoC modules comprise a processor subsystem and a hardware logic subsystem. The processor subsystem and hardware logic subsystem are in communication with one another, and transmit event messages between one another. The processor subsystem executes software actors, while the hardware logic subsystem includes hardware actors, the software actors and hardware actors conform to an event-driven architecture, such that the software actors receive and generate event messages and the hardware actors receive and generate event messages.

Apparatus, systems, and methods for analyzing data are described. The data can be analyzed using a hierarchical structure. One such hierarchical structure can comprise a plurality of layers, where each layer performs an analysis on input data and provides an output based on the analysis. The output from lower layers in the hierarchical structure can be provided as inputs to higher layers. In this manner, lower layers can perform a lower level of analysis (e.g., more basic/fundamental analysis), while a higher layer can perform a higher level of analysis (e.g., more complex analysis) using the outputs from one or more lower layers. In an example, the hierarchical structure performs pattern recognition.

A method of implementations includes receiving, by a processing device executing a unified storage manager (USM), an update package comprising a configuration file for a storage service to add to the USM, adding, by the processing device, the configuration file to a set of configuration files maintained by the USM, responsive to detecting the addition of the configuration file, causing, by the processing device, a re-load of the set of configuration files at the USM without a shutdown and re-start of the USM, loading, by the processing device, the configuration file in the USM, and initializing, by the processing device, an adaptor component for the storage service at the USM, the adaptor component comprising a set of application programming interface (API) methods for the USM to communicate with the storage service.

An optimized reconfiguration algorithm based on dynamic voltage and frequency scaling (DVFS) is provided, which mainly has the following contributions. The optimized reconfiguration algorithm based on DVFS proposes a DVFS-based reconfiguration method, which schedules user tasks according to a degree of parallelism (DOP) of the user tasks so as to reconfigure more parallel user tasks, thereby achieving higher reliability. The optimized reconfiguration algorithm based on DVFS proposes a K-means-based heuristic approximation algorithm, which minimizes the delay of the DVFS-based reconfiguration scheduling algorithm. The optimized reconfiguration algorithm based on DVFS proposes a K-means-based method, which reduces memory overhead caused by DVFS-based reconfiguration scheduling. The optimized reconfiguration algorithm based on DVFS improves the reliability of a field programmable gate array (FPGA) system and minimizes the area overhead of a hardware circuit.

A method of processing partitions of a tensor in a target order includes receiving, by a reorder unit and from two or more producer units, a plurality of partitions of a tensor in a first order that is different from the target order, storing the plurality of partitions in the reorder unit, and providing, from the reorder unit, the plurality of partitions in the target order to one or more consumer units. In an example, the one or more consumer units process the plurality of partitions in the target order.

An FPGA system includes: an FPGA configured such that a partial reconfiguration is executable; and an external storage medium that is positioned outside of the FPGA and stores configuration data that is readable by the FPGA. The external storage medium stores first configuration data indicating a configuration of a circuit that is not subject to the partial reconfiguration and a second configuration data indicating a configuration of a circuit that is subject to the partial reconfiguration. The first configuration data includes configuration data indicating a configuration of a reconfiguration activation circuit for reading the second configuration data from the external storage medium and deploying the configuration indicated by the second configuration data.