An enhanced TL-TCAM lookup-table hardware search engine includes a plurality of enhanced TL-TCAM cell circuits. There are m enhanced TL-TCAM cells circuits connected in parallel to form a sub-segment circuit. The word line WL, match line ML and ML_x of each enhanced TL-TCAM cell circuit in the sub-segment circuit are respectively short-connected together, the match line ML is connected to the drain electrode of an N-type transistor N15, ML_x is connected to the gate electrode of the N-type transistor N15, and the source electrode of the N-type transistor N15 is connected to ground, ML_x is connected to the drain electrode of an N-type transistor N14, the source electrode of the N-type transistor N14 is connected to ground, and the gate electrode of the N-type transistor N14 is connected to the signal line OneX_in-Sement_b, a plurality of sub-segment circuits are connected in parallel to form a word circuit.

An algorithmic TCAM based ternary lookup method is provided. The method stores entries for ternary lookup into several sub-tables. All entries in each sub-table have a sub-table key that includes the same common portion of the entry. No two sub-tables are associated with the same sub-table key. The method stores the keys in a sub-table keys table in TCAM. Each key has a different priority. The method stores the entries for each sub-table in random access memory. Each entry in a sub-table has a different priority. The method receives a search request to perform a ternary lookup for an input data item. A ternary lookup into the ternary sub-table key table stored in TCAM is performed to retrieve a sub-table index. The method performs a ternary lookup across the entries of the sub-table associated with the retrieved index to identify the highest priority matched entry for the input data item.

A table lookup apparatus has a content-addressable memory (CAM) based device and a scope mask circuit. The CAM based device has CAM entries that are used to vertically store a plurality of tables in a word-wise aggression fashion, wherein the CAM entries are responsive to a valid bit input including valid bits of the CAM entries, and a CAM entry is invalid when receiving a corresponding valid bit set by a predetermined logic value. The scope mask circuit masks a portion of the valid bit input by assigning the predetermined logic value to each valid bit included in the portion of the valid bit input, wherein the portion of the valid bit input corresponds to non-selected table (s).

The present disclosure provides method and system for automatic monitoring and control of compliance of one or more operations of smart city infrastructure in real-time. Compliance management system detects conflict initiated by compliance violation of one or more operations related to plurality of registered participants of smart city infrastructure. The compliance management system identifies policies associated with compliance of one or more operations and determines criticality of compliance of one or more operations based on one or more policies. The compliance management system determines relationship among compliance of one or more operations based on interdependencies among the operations. Further, the compliance management system generates action plan based on availability of one or more resources corresponding to compliance of one or more operations in real-time and relationship. Finally, the compliance management system monitors execution action plan to remove the conflict and achieve compliance of one or more operations based on criticality.

A communication apparatus comprises a CAM, an action determination unit, and a CAM diagnosis unit. The CAM includes, a plurality of entries each storing therein at least a portion of header information of frame, and a search circuit for each entry configured to determine whether or not a search key matches data stored at the entry. The search key is correlated with information indicating whether or not an entry matching the search key and an expected value of a search result including identification information of an entry matching the search key. The CAM diagnosis unit causes the CAM to search for an entry matching the search key. The CAM diagnosis unit diagnoses a failure occurring at the search circuit of an entry to be the test object when the result of the search does not match the expected value of a search result correlated to the search key.

Embodiments are directed to managing character encoding. A plurality characters that are each encoded as code units based on a character code may be provided such that the code units for each character represents a code point of a character encoding scheme. An encoding model may be determined based on the character code, one or more processor features, and a target character code. Process features may be employed to transform the code units into target code units based on the encoding model such that the target code units are based on the target character code and such that the target code units encode the code point for each character. The plurality of target characters may be provided to a target stream such that each target character may be encoded as the target code units.

A parallel turbine ternary content addressable memory includes one or more atoms in each of one or more rows, wherein each of the one or more atoms includes a memory with N addresses and a width of M logical lookup entries, wherein N and M are integers, one or more result registers, each with a width of M, wherein a number of the one or more result registers equals a number of one or more keys each with a length of N, and a read pointer configured to cycle through a row of the N addresses per clock cycle for comparison between the M logical entries and the one or more keys with a result of the comparison stored in an associated result register for each of the one or more keys.

In an edge computing system deployment, a system includes memory and processing circuitry coupled to the memory. The processing circuitry is configured to obtain a workflow execution plan that includes workload metadata defining a plurality of workloads associated with a plurality of edge service instances executing respectively on one or more edge computing devices. The workload metadata is translated to obtain workload configuration information for the plurality of workloads. The workload configuration information identifies a plurality of memory access configurations and service authorizations identifying at least one edge service instance authorized to access one or more of the memory access configurations. The memory is partitioned into a plurality of shared memory regions using the memory access configurations. A memory access request for accessing one of the shared memory regions is processed based on the service authorizations.

In one embodiment, an associative memory is built using multiple cascaded associative memory blocks, with stored lookup words spanning a same or different numbers of associative memory blocks. A first lookup operation is performed by a first associative memory to generate first matching indications of associative entries of the first associative memory that match both the first lookup word and the first lookup type. A second lookup operation is performed by an end associative memory to generate end matching indications of associative entries of the end associative memory that match both the end lookup word and the end of word lookup type. A final lookup result indicating a matching multi-block spanning associative memory entry based on the first matching indications and the end matching indications is determined and signaled by the associative memory is built using multiple cascaded associative memory blocks.

The present invention relates to a semiconductor device capable of providing extensibility in the entry direction and bit direction of a search table. The semiconductor device includes: a block search circuit that searches each of a plurality of block tables into which a search table, which is configured in the entry direction and in the bit direction, is divided in the entry direction and in the bit direction; a circuit that combines the search results of the block search circuits in the bit direction; and a control circuit that inputs a search key as well as the outputs of the combining circuits, and outputs hit information.