Patent classifications
G06F21/755
INTEGRATED CIRCUIT DEVICE WITH PROTECTION AGAINST MALICIOUS ATTACKS
An integrated circuit device includes a semiconductor substrate layer and at least one active layer including electronic components and supported by the semiconductor substrate layer. The semiconductor substrate layer and the at least one active layer are sandwiched between two protective layers acting as physical obstacles to prevent the passage of radiations. In addition, the two protective layers are electrically connected to a detection circuit that can monitor an electrical information of the protective layers and detect a physical attack of at least one of the two protective layers, based on the monitored electrical information.
STORAGE DEVICE AND DATA ACCESS METHOD
A storage device and a data access method are provided. The storage device includes a primary storage unit and at least one additional unit. The primary storage unit includes: a primary memory element configured to store secret data and a primary access unit configured to receive an external access command. Each additional unit is configured to receive the external access command. Each additional unit includes: an additional memory element configured to store non-specific data, a local access generation element configured to trigger generating an internal access command based on the external access command, and an additional access unit configured to receive a local access command. The primary storage unit and each additional unit are coupled to a same power rail and a connection wire to simultaneously receive the external access command to parallelly (simultaneously) access the secret data and the non-specific data stored in each additional unit.
Platform neutral data encryption standard (DES) cryptographic operation
Systems and methods for protecting block cipher computation operations from external monitoring attacks. An example apparatus for implementing a block cipher may comprise a memory device to store instructions for computing a block cipher; and a processing device coupled to the memory device. The processing device performs a Data Encryption Standard (DES) cryptographic operation with multiple rounds of a Feistel structure, each round including a substitution function and a transformation function that combines an expansion function and a permutation function into a single operation. The transformation function transforms a first input portion of an internal state of the respective round and a second input portion of the internal state into a first output portion and a second output portion of data. The second output portion is equal to the first input portion and the first output portion is dependent on a combined permutation output from the transformation function.
Device and method for electronic circuit power
The present invention concerns an electronic circuit power supply device, configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node, a first branch of a current mirror conducting the third current; flow a fourth constant current through a third conductor connected to the node; consume a fifth current that is an image of the third current; and regulate a potential of the node by acting on a gate potential of a transistor electrically in series with a second branch of the current mirror.
SYSTEM ON CHIP INCLUDING A PVT SENSOR AND CORRESPONDING PVT SENSING METHOD
A system-on-chip includes a process-voltage-temperature (PVT) sensor with a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to variations in semiconductor material, operating supply voltage and operating temperature of the system-on-chip. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. A warning signal is generated in response to the comparison where there is a detection of discrepancy between the initiated patterned digital signal and the propagated patterned digital signal.
CHIP WITH POWER-GLITCH DETECTION
A chip with power-glitch detection is provided, which includes a power terminal receiving power, an inverter, and a back-up power storage device coupled to the power terminal. The inverter has an input terminal coupled to the power terminal. The back-up power storage device transforms the power to back-up power. The inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the inverter.
EVENT DETECTION CONTROL DEVICE AND METHOD FOR CIRCUIT SYSTEM CONTROLLED BY PULSE WAVE MODULATION SIGNAL
An event detection controller for a circuit system controlled by a pulse wave modulation signal, can perform a specific event handling when a specific event is detected, wherein the specific event handling includes stopping a pulse wave modulation device, starting up the stopped pulse wave modulation device, controlling the pulse wave modulation device to change the pulse wave modulation signal, outputting a wake-up signal to wake up the circuit system, controlling the pulse detector to change its detection configuration, changing a cumulative occurrences number of the specific pattern of an event discrimination module, outputting a control signal or a first data signal to a peripheral device through a bus connected to an event response module and/or requesting the peripheral device to send a second data signal through the bus.
Remote attestation of system integrity
An apparatus and system for remote attestation of a power delivery network is disclosed. Embodiments of the disclosure enable remote attestation of the power delivery network by storing a trusted golden reference waveform in secure memory. The trusted golden reference waveform characterizes a power delivery network in response to a load generated on the power delivery network. A remote cloud server generates a server-generated remote attestation of the power delivery network by receiving an attestation packet from the power delivery network and verifying whether the attestation packet is consistent with an expected power delivery network identity.
PARAMETER CHECKING SYSTEM AND PARAMETER CHECKING METHOD
A parameter checking method includes substituting a plurality of initial parameters into a data integrity algorithm to obtain syndrome data using a processor, and using a hardware cipher to calculate a calculation result based on the data integrity algorithm based on a plurality of calculation parameters corresponding to the initial parameters. Moreover, when the processor determines that the syndrome data is not the same as the calculation result, the processor outputs a hacker attack message, indicating that at least one of the calculation parameters has been tampered with.
Electromagnetic pulse detection
An embodiment integrated circuit includes a first electromagnetic pulse detection device that comprises a first loop antenna formed in an interconnection structure of the integrated circuit, a first end of the first antenna being connected to a first node of application of a power supply potential and a second end of the antenna being coupled to a second node of application of the power supply potential, and a first circuit connected to the second end of the first antenna and configured to output a first signal representative of a comparison of a first current in the first antenna with a first threshold.