One embodiment described herein provides a system and method for simulating behavior of a quantum circuit that includes a plurality of quantum gates. During operation, the system receives information that represents the quantum circuit and constructs an undirected graph corresponding to the quantum circuit. A respective vertex within the undirected graph corresponds to a distinct variable in a Feynman path integral used for computing amplitude of the quantum circuit, and a respective edge corresponds to one or more quantum gates. The system identifies a vertex within the undirected graph that is coupled to at least two two-qubit quantum gates; simplifies the undirected graph by removing the identified vertex, thereby effectively removing the two-qubit quantum gates coupled to the identified vertex; and evaluates the simplified undirected graph, thereby facilitating simulation of the behavior of the quantum circuit.

One embodiment described herein provides a system and method for simulating behavior of a quantum circuit that includes a plurality of quantum gates. During operation, the system receives information that represents the quantum circuit and constructs an undirected graph corresponding to the quantum circuit. A respective vertex within the undirected graph corresponds to a distinct variable in a Feynman path integral used for computing amplitude of the quantum circuit, and a respective edge corresponds to one or more quantum gates. The system identifies a vertex within the undirected graph that is coupled to at least two two-qubit quantum gates; simplifies the undirected graph by removing the identified vertex, thereby effectively removing the two-qubit quantum gates coupled to the identified vertex; and evaluates the simplified undirected graph, thereby facilitating simulation of the behavior of the quantum circuit.

An method, a computer readable medium and a system for an automated design of a controllable oscillator are provided, wherein the method includes: receiving a set of input data through an automated design procedure, wherein the set of input data includes an initial circuit description file and a criteria file, and the initial circuit description file records initial values of parameters of one or more components within the controllable oscillator; performing simulation according to the set of input data through the automated design procedure to generate a simulation result; and selectively modifying at least one parameter within the parameters of the one or more components according to the simulation result through the automated design procedure. In addition, in the process of modifying the at least one parameter, connection relationships of all components within the controllable oscillator are unchanged.

An method, a computer readable medium and a system for an automated design of a controllable oscillator are provided, wherein the method includes: receiving a set of input data through an automated design procedure, wherein the set of input data includes an initial circuit description file and a criteria file, and the initial circuit description file records initial values of parameters of one or more components within the controllable oscillator; performing simulation according to the set of input data through the automated design procedure to generate a simulation result; and selectively modifying at least one parameter within the parameters of the one or more components according to the simulation result through the automated design procedure. In addition, in the process of modifying the at least one parameter, connection relationships of all components within the controllable oscillator are unchanged.

A power electronic circuit fault diagnosis method based on Extremely randomized trees (ET) and Stack Sparse auto-encoder (SSAE) algorithm includes the following. First, collect the fault signal and extract fault features. Then, reduce the dimensionality of fault features by calculating the importance value of all features using ET algorithm. A proportion of the features to be eliminated is determined, and a new feature set is obtained according the value of importance. Further extraction of fault features is carried by using SSAE algorithm, and hidden layer features of the last sparse auto-encoder are obtained as fault features after dimensionality reduction. Finally, the fault samples in a training set and a test set are input to the classifier for training to obtain a trained classifier. And mode identification, wherein the fault of the power electronic circuit is identified and located by the training classifier.

A power electronic circuit fault diagnosis method based on Extremely randomized trees (ET) and Stack Sparse auto-encoder (SSAE) algorithm includes the following. First, collect the fault signal and extract fault features. Then, reduce the dimensionality of fault features by calculating the importance value of all features using ET algorithm. A proportion of the features to be eliminated is determined, and a new feature set is obtained according the value of importance. Further extraction of fault features is carried by using SSAE algorithm, and hidden layer features of the last sparse auto-encoder are obtained as fault features after dimensionality reduction. Finally, the fault samples in a training set and a test set are input to the classifier for training to obtain a trained classifier. And mode identification, wherein the fault of the power electronic circuit is identified and located by the training classifier.

A method and apparatus for device simulation are provided. The method includes: establishing a simulation model of a to-be-detected device, where the to-be-detected device includes a first resistor and a parasitic resistor, the parasitic resistor includes a second resistor and a contact resistor, the first resistor is a bulk resistor of the to-be-detected device, the second resistor is a terminal resistor of the to-be-detected device, and the contact resistor is an equivalent resistor of a contact plug on the to-be-detected device; determining temperature coefficients of resistance corresponding to the first resistor, the second resistor, and the contact resistor, and adding the temperature coefficients of resistance to the simulation model; and performing device simulation of Simulation Program with Integrated Circuit Emphasis (SPICE) according to the simulation model.

A method and apparatus for device simulation are provided. The method includes: establishing a simulation model of a to-be-detected device, where the to-be-detected device includes a first resistor and a parasitic resistor, the parasitic resistor includes a second resistor and a contact resistor, the first resistor is a bulk resistor of the to-be-detected device, the second resistor is a terminal resistor of the to-be-detected device, and the contact resistor is an equivalent resistor of a contact plug on the to-be-detected device; determining temperature coefficients of resistance corresponding to the first resistor, the second resistor, and the contact resistor, and adding the temperature coefficients of resistance to the simulation model; and performing device simulation of Simulation Program with Integrated Circuit Emphasis (SPICE) according to the simulation model.

A simulation system and a method thereof are disclosed. In the simulation system, a system power transmission model, and analog current time-domain model and digital current time-domain model are connected to obtain power noise generated after a supply current is obtained; jitter time-domain information of each interface connection circuit model under the power noise is obtained based on transmission of a clock signal outputted from a phase lock loop, by a simulation program; next, a voltage step response of a voltage measurement point when a clock terminal of each interface connection circuit model receives an ideal signal, is simulated by the simulation program to generate a first voltage time-domain model; a system waveform is generated based on the jitter time-domain information of each interface connection circuit model under the power noise, the first voltage time-domain model and data transmission, thereby obtaining an eye diagram and time-domain jitter distribution.

A simulation system and a method thereof are disclosed. In the simulation system, a system power transmission model, and analog current time-domain model and digital current time-domain model are connected to obtain power noise generated after a supply current is obtained; jitter time-domain information of each interface connection circuit model under the power noise is obtained based on transmission of a clock signal outputted from a phase lock loop, by a simulation program; next, a voltage step response of a voltage measurement point when a clock terminal of each interface connection circuit model receives an ideal signal, is simulated by the simulation program to generate a first voltage time-domain model; a system waveform is generated based on the jitter time-domain information of each interface connection circuit model under the power noise, the first voltage time-domain model and data transmission, thereby obtaining an eye diagram and time-domain jitter distribution.