Embodiments include dynamic control of coverage by a verification testbench. Aspects include obtaining a design under test to be verified by the verification testbench and obtaining one or more testcases for execution by the verification testbench on the design under test. Aspects also include obtaining a plurality of triggers corresponding to the design under test, wherein each of the plurality of triggers includes an activation condition, a deactivation condition and a coverage. Aspects further include simulating, by the verification testbench, execution of the one or more testcases by the design under test. Based on detecting the activation condition of one of the plurality of triggers, aspects also include recording, in a coverage database, data specified in the coverage corresponding the one of the plurality of triggers until the deactivation condition is detected.

Embodiments include dynamic control of coverage by a verification testbench. Aspects include obtaining a design under test to be verified by the verification testbench and obtaining one or more testcases for execution by the verification testbench on the design under test. Aspects also include obtaining a plurality of triggers corresponding to the design under test, wherein each of the plurality of triggers includes an activation condition, a deactivation condition and a coverage. Aspects further include simulating, by the verification testbench, execution of the one or more testcases by the design under test. Based on detecting the activation condition of one of the plurality of triggers, aspects also include recording, in a coverage database, data specified in the coverage corresponding the one of the plurality of triggers until the deactivation condition is detected.

One example method includes evaluating code of a quantum circuit, estimating one or more runtime statistics concerning the code, generating a recommendation based on the one or more runtime statistics, and the recommendation identifies one or more resources recommended to be used to execute the quantum circuit, checking availability of the resources for executing the quantum circuit, allocating resources, when available, sufficient to execute the quantum circuit, and using the allocated resources to execute the quantum circuit.

Systems, computer-implemented methods, and computer program products to facilitate sampling of an operator in a quantum system are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a cache component that caches a probability distribution and a quantum state of one or more Kraus operators in a quantum circuit. The computer executable components can further comprise a simulator component that simulates one or more shots of the quantum circuit based on the probability distribution and the quantum state of the one or more Kraus operators. The one or more shots are indicative of one or more algorithm execution instances.

The present disclosure generally relates to an analog mixed-signal (AMS) design verification system. In particular, the present disclosure relates to a system and method for system verification. One example method includes: obtaining an electronic representation of the circuit design; generating at least a portion of a waveform using the electronic representation of the circuit to obtain a first segment of the waveform associated with the circuit; converting, via the one or more processors, one or more measurement functions to code for performing the one or more computations on the first segment of the waveform; performing one or more computations on the first segment of the waveform using the code; and identifying when a behavior of the circuit violates a design specification based on whether a result of the one or more computations meets a threshold.

The present disclosure generally relates to an analog mixed-signal (AMS) design verification system. In particular, the present disclosure relates to a system and method for system verification. One example method includes: obtaining an electronic representation of the circuit design; generating at least a portion of a waveform using the electronic representation of the circuit to obtain a first segment of the waveform associated with the circuit; converting, via the one or more processors, one or more measurement functions to code for performing the one or more computations on the first segment of the waveform; performing one or more computations on the first segment of the waveform using the code; and identifying when a behavior of the circuit violates a design specification based on whether a result of the one or more computations meets a threshold.

A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the subset of leaf nodes is generated. The bypass module is generated in response to detecting presence of the subset of leaf nodes in the electronic design with input/output signaling of more than two values. The bypass module facilitates communication between the testbench and the subset of leaf nodes. Leaf nodes other than the subset of leaf nodes communicate with the testbench without communicating through the bypass module.

A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the subset of leaf nodes is generated. The bypass module is generated in response to detecting presence of the subset of leaf nodes in the electronic design with input/output signaling of more than two values. The bypass module facilitates communication between the testbench and the subset of leaf nodes. Leaf nodes other than the subset of leaf nodes communicate with the testbench without communicating through the bypass module.

Samples of metrics measured on physical devices are selected from a larger number of samples. The samples are selected based on the distributions of the measured metrics. A set of model instances are constructed that correspond to the selected set of samples. The model instances have parameters, which are set such that simulation of the model instances using the parameters predicts metrics that match the measured metrics from the set of samples. The principal components of the variances of the parameters is calculated. Non-linear models are fitted to the parameter variances as a function of the principal components. Statistical variations of the principal components are applied to the non-linear models to yield statistical variations in the parameters; and these are applied to simulations of model instances to yield statistical variations of a property of the device being simulated.

Samples of metrics measured on physical devices are selected from a larger number of samples. The samples are selected based on the distributions of the measured metrics. A set of model instances are constructed that correspond to the selected set of samples. The model instances have parameters, which are set such that simulation of the model instances using the parameters predicts metrics that match the measured metrics from the set of samples. The principal components of the variances of the parameters is calculated. Non-linear models are fitted to the parameter variances as a function of the principal components. Statistical variations of the principal components are applied to the non-linear models to yield statistical variations in the parameters; and these are applied to simulations of model instances to yield statistical variations of a property of the device being simulated.