A static timing analysis system for finding and reporting timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use exhaustive path-based analysis (EPBA) that is informed by infinite-depth path-based analysis (IPBA) to provide analysis results that are driven full-depth, in contrast to conventional EPBA systems and methods, which can terminate after reaching a maximum depth of analysis as a way of avoiding prolonged or infinite runtimes. The IPBA-driven full-depth EPBA functions for hold-mode as well as setup-mode analysis and achieves reduced pessimism as compared to systems or methods employing IPBA alone, and more complete analysis of designs as compared to systems or methods employing EPBA alone. Improved IPBA signal merging using multidimensional zones for thresholding of signal clustering mitigates the occasional optimism of IPBA.

Disclosed is a method and apparatus that determines receiver capacitance values for a receiver cell from a multi-segment receiver capacitance model (C1Cn) model. Values for receiver capacitance are determined from a Composite Current Source for Noise (CCSN) model under conditions used to attain receiver capacitance values for the C1Cn model Difference values for the difference between the values from the CCSN model and from the C1Cn model are determined. Calibration factors are iteratively applied to parameters of the CCSN model to obtain a minimum difference value for difference between receiver capacitance values from the CCSN model and receiver capacitance values from the C1Cn model. Calibration factor values that result in the difference value being within an acceptable range are stored.

Embodiments include herein are directed towards a method for static timing analysis. Embodiments included herein may include providing, using at least one processor, a database of predefined script tags and causing a display of a script at a graphical user interface. Embodiments may also include receiving an insertion of at least one tag from the database within the script and generating one or more timing reports based upon, at least in part, the script and the at least one tag.

Embodiments include herein are directed towards a method for static timing analysis. Embodiments included herein may include providing, using at least one processor, a database of predefined script tags and causing a display of a script at a graphical user interface. Embodiments may also include receiving an insertion of at least one tag from the database within the script and generating one or more timing reports based upon, at least in part, the script and the at least one tag.

A device and a method for integrated circuit assistance design, and a method for constructing an electrical performance gradient model are provided. The device includes a database and a processor. The database has an electrical performance gradient model. The electrical performance gradient model represents a gradient distribution of an electrical performance in a wafer. The processor is coupled to the database. The processor analyzes a designed circuit by using the electrical performance gradient model.

A device and a method for integrated circuit assistance design, and a method for constructing an electrical performance gradient model are provided. The device includes a database and a processor. The database has an electrical performance gradient model. The electrical performance gradient model represents a gradient distribution of an electrical performance in a wafer. The processor is coupled to the database. The processor analyzes a designed circuit by using the electrical performance gradient model.

A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.

A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.

Mechanisms are provided for optimizing an integrated circuit device design to obfuscate emissions corresponding to internal logic states of the integrated circuit device design. A first integrated circuit (IC) device design data structure is received and parsed to identify at least one instance of an obfuscation indicator in the data of the IC device design data structure. At least one IC logic element is marked, in the IC device design, which is associated with the at least one instance of the obfuscation indicator. At least one emission obfuscation optimization is applied to the marked at least one IC logic element to obfuscate emissions from the marked at least one IC logic element and generate an emissions obfuscated IC device design data structure. The emissions obfuscated IC device design data structure is output for fabrication of an IC device in accordance with the emissions obfuscated IC device design data structure.

Mechanisms are provided for optimizing an integrated circuit device design to obfuscate emissions corresponding to internal logic states of the integrated circuit device design. A first integrated circuit (IC) device design data structure is received and parsed to identify at least one instance of an obfuscation indicator in the data of the IC device design data structure. At least one IC logic element is marked, in the IC device design, which is associated with the at least one instance of the obfuscation indicator. At least one emission obfuscation optimization is applied to the marked at least one IC logic element to obfuscate emissions from the marked at least one IC logic element and generate an emissions obfuscated IC device design data structure. The emissions obfuscated IC device design data structure is output for fabrication of an IC device in accordance with the emissions obfuscated IC device design data structure.