A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.

Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

A method of designing an interconnect structure of a semiconductor apparatus is provided. The interconnect structure includes interconnection layers sequentially stacked on a semiconductor substrate, and each of the interconnection includes dummy metal patterns and main metal patterns. The method includes: determining a layout of the main metal patterns included in each of the plurality of interconnection layers; determining a number of interconnection layers in the plurality of interconnection layers; and determining a layout of the dummy metal patterns included in each of the plurality of interconnection layers based on the determined layout of the main metal patterns and the determined number of interconnection layers.

A method of designing an interconnect structure of a semiconductor apparatus is provided. The interconnect structure includes interconnection layers sequentially stacked on a semiconductor substrate, and each of the interconnection includes dummy metal patterns and main metal patterns. The method includes: determining a layout of the main metal patterns included in each of the plurality of interconnection layers; determining a number of interconnection layers in the plurality of interconnection layers; and determining a layout of the dummy metal patterns included in each of the plurality of interconnection layers based on the determined layout of the main metal patterns and the determined number of interconnection layers.

A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the CSD conductors; VG structures in the transistor layer, and over the active area; and a first gate-signal-carrying (GSC) conductor in an M_1st layer that is over the transistor layer, and that is over the active area; and wherein long axes correspondingly of the active area and the first GSC conductor extend substantially in a first direction; and long axes correspondingly of the CSD conductors and the gate conductors extend substantially in a second direction, the second direction being substantially perpendicular to the first direction.

A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the CSD conductors; VG structures in the transistor layer, and over the active area; and a first gate-signal-carrying (GSC) conductor in an M_1st layer that is over the transistor layer, and that is over the active area; and wherein long axes correspondingly of the active area and the first GSC conductor extend substantially in a first direction; and long axes correspondingly of the CSD conductors and the gate conductors extend substantially in a second direction, the second direction being substantially perpendicular to the first direction.

A semiconductor device includes a cell. The cell includes an active area, gates, at least one gate via and at least one contact via. The active area includes forbidden regions. The gates are disposed across the active area. The at least one gate via is coupled with one of the gates. The at least one contact via is coupled with at least one conductive segment each corresponding to a source/drain of a transistor. In a layout view, one of the forbidden regions abuts a region of an abutted cell in which at least one of a gate via or a contact via of the abutted cell is disposed. In a layout view, the least one of the at least one gate via or the at least one contact via is arranged within the active area and outside of the forbidden regions. A method is also disclosed herein.

A semiconductor device includes a cell. The cell includes an active area, gates, at least one gate via and at least one contact via. The active area includes forbidden regions. The gates are disposed across the active area. The at least one gate via is coupled with one of the gates. The at least one contact via is coupled with at least one conductive segment each corresponding to a source/drain of a transistor. In a layout view, one of the forbidden regions abuts a region of an abutted cell in which at least one of a gate via or a contact via of the abutted cell is disposed. In a layout view, the least one of the at least one gate via or the at least one contact via is arranged within the active area and outside of the forbidden regions. A method is also disclosed herein.

Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.