A guard sensor injects a multi-GHz (multi giga-bit) guard signal along a guard signal transmission path above an observable knee in the amplitude response of the path to define a guarded region and to detect physical or electromagnetic intrusions of that guarded region. At frequencies above the knee, the signal transmission path exhibits increasingly non-linear and even chaotic behavior that improves the overall sensitivity of the sensor and its ability to detect slight changes in the distributed transmission parameters that characterize circuit devices, signal paths and signals. The guarded region may be used to protect a combination of circuit devices, physical connections, interfaces, high and low frequency signal transmission paths and signals.

Disclosed is a wireless tamper device (WTD). The WTD includes a transmitter, multi-layer probe, processing device, and power supply. The processing device is in signal communication with the multi-layer probe and the power supply is in signal communication with the transmitter and processing device. The processing device includes a processor and a computer-readable medium (CRM). The CRM has encoded thereon computer-executable instructions to cause the processor to initiating a tamper state to untampered, detect a physical trigger on the multi-layer probe, and set the tamper state to tampered in response to detecting the physical trigger.

Disclosed is a wireless tamper device (WTD). The WTD includes a transmitter, multi-layer probe, processing device, and power supply. The processing device is in signal communication with the multi-layer probe and the power supply is in signal communication with the transmitter and processing device. The processing device includes a processor and a computer-readable medium (CRM). The CRM has encoded thereon computer-executable instructions to cause the processor to initiating a tamper state to untampered, detect a physical trigger on the multi-layer probe, and set the tamper state to tampered in response to detecting the physical trigger.

Tamper-respondent assemblies and methods of fabrication are provided which include at least one tamper-respondent sensor and a detector. The at least one tamper-respondent sensor includes conductive lines which form, at least in part, at least one tamper-detect network of the tamper-respondent sensor(s). The detector monitors the tamper-respondent sensor(s) by applying an electrical signal to the conductive lines of the at least one tamper-respondent sensor to monitor over time for a non-linear conductivity change indicative of a tamper event at the tamper-respondent sensor(s). For instance, the detector may monitor a second harmonic of the electrical signal applied to the conductive lines for the non-linear conductivity change indicative of the tamper event, such as an attempted shunt of one or more conductive lines of the tamper-respondent sensor(s).

The invention relates to a seal containing a substrate which can be applied to an object to be sealed, so that said seal is changed when it is removed without authorization, wherein the substrate contains or comprises a polymer and/or a glass and at least one optical waveguide is arranged in the substrate, at least one first Bragg grating being arranged in said optical waveguide, wherein the substrate has a thickness of less than 200 m. The invention further relates to a system having a seal of this kind and having an evaluation device, and also to a sealing method.

Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure to circuit board protection. The tamper-respondent assemblies include a circuit board, and an electronic enclosure mounted to the circuit board and facilitating enclosing at least one electronic component within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and the tamper-respondent electronic circuit structure includes a tamper-respondent circuit. An adhesive is provided to secure, in part, the electronic enclosure to the circuit board. The adhesive contacts, at least in part, the tamper-respondent circuit so that an attempted separation of the electronic enclosure from the circuit board causes the adhesive to break the tamper-respondent circuit, facilitating detection of the separation by a monitor circuit of the tamper-respondent electronic circuit structure.

Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.