A display device includes a display substrate and a backplane substrate. The display substrate includes an array of micro-LEDs forming individual pixels. The backplane substrate includes a plurality of pixel logic hardware modules. Each pixel logic hardware module includes a local memory element configured to store a multi-bit pixel intensity value of a corresponding micro-LED for an image frame. The backplane substrate is bonded to a backside of the display substrate such that the pixel logic hardware modules are physically aligned behind the array of micro-LEDs and each pixel logic hardware module is electrically connected to a micro-LED of the corresponding pixel.

A display device includes a display layer including a plurality of light-emitting devices and a plurality of switching devices in a one-to-one correspondence with the light-emitting devices, the plurality of light-emitting devices and the plurality of switching devices forming a monolithic structure, and a driving layer, wherein the plurality of light-emitting devices and the plurality of switching devices corresponding to the plurality of light-emitting devices are grouped into pixels and then arranged in the display layer, and the driving layer includes a plurality of driving devices configured to apply at least one driving signal to the display layer.

A display substrate has a display area and a peripheral area around the display area. The display substrate includes a plurality of sub-pixels arranged in an array in the display area, and an interface circuit, at least two serial-to-parallel converters and at least one display driver that are in the peripheral area. The interface circuit is configured to receive target data including a plurality of serial display data. A serial-to-parallel converter in the at least two serial-to-parallel converters is used to convert the plurality of serial display data into parallel display data. The serial-to-parallel converter is electrically connected to one display driver to provide the parallel display data to the display driver. The display driver is used to output display driving signals to a plurality of sub-pixels according to the parallel display data.

A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.

A display system comprising a plurality of display controller circuits controlling a like number of independent segments of pixel drive circuits of a backplane. Each pixel drive circuit comprises a memory element and associated pixel drive circuitry. The segments of the backplane may be organized vertically. The word line for the memory cells of a first segment of pixel drive circuits passes underneath a second segment of pixel drive circuits without directly interacting with the pixel drive circuits of the second segment in order to reach the pixel drive circuits of the first segment. The plurality of display controller circuits operate asynchronously but are kept at the same frame rate by an external signal such as Vsync.

Provided are a pixel having two contacting points and an operating method of the pixel. The pixel includes a positive power terminal and a negative power terminal which are related to power required for driving of a pixel driving circuit unit driving a plurality of light-emitting elements, wherein the positive power terminal is connected to a data driving circuit, and the negative power terminal is connected to a scan driving circuit. The pixel may be driven according to a potential difference between a signal output from the data driving circuit and a signal output from the scan driving circuit.

A display device includes: a cell matrix including a first cell line and a second cell line, wherein the first cell line includes first cells sharing first row lines, and the second cell line includes second cells sharing second row lines; a redundancy integrated circuit including a redundancy cell line including redundancy cells, wherein the redundancy cells share a third row line and are connected to the first and second cells through a plurality of column lines and a plurality of connection lines; and a display driver integrated circuit (DDI) configured to replace the first cell line or the second cell line with the redundancy cell line through the first row lines, the second row lines, and the third row line based on whether the first and second cell lines include a bad cell.

A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

A method to generate pixel control signal more rapidly and with less overhead is disclosed. The method generates pixel control signals for a block of pixels having a first pixel and a second pixel. A base control signal that is shared by the block of pixels is generated. A first sharpening control signal for the first pixel is generated and a second sharpening control signal for the second pixel is generated. The first pixel control signal is generated using the first sharpening signal and the base control signal. The second pixel control signal is generated using the second sharpening signal and the base control signal. The base control signal is stored in a first memory cell; the first sharpener control signal is stored in a second memory cell; and the second sharpener control signal is stored in a third memory cell.

A display is created using “smart pixels.” A smart pixel is a pixel of a display that integrates the pixel pipeline as part of the pixel, rather than using separate integrated circuits. A smart pixel may be based on an integrated stack that includes light emitting elements, an external data contact for receiving digital data for that pixel, and also the pixel pipeline from the digital data to the light emitting elements.