The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure comprises a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element, a clock generator configured to generate a plurality of clock signals each corresponding to each of a plurality of subframes constituting a frame, and a parallel to serial converter configured to convert the plurality of clock signals to a serial clock signal and transfer the serial clock signal to the pixel unit, and wherein the pixel circuit of each pixel includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of the plurality of subframes and a second pixel circuit configured to store bit values of image data in the frame and generate the control signal based on the stored bit values and the serial clock signal such that each subframe included in the frame is controlled according to each bit value.

A micro-light emitting diode (micro-LED) display backplane includes a plurality of macro-pixels. Each macro-pixel includes: a contiguous two-dimensional (2-D) array of bitcells storing display data bits for driving a set of micro-LEDs of a 2-D array of micro-LEDs; and drive circuits configured to generate, based on the display data bits stored in the contiguous 2-D array of bitcells, pulse-width modulated (PWM) drive signals for driving the set of micro-LEDs of the 2-D array of micro-LEDs. In one example, the plurality of macro-pixels is grouped into a plurality of sub-arrays, where each sub-array of the plurality of sub-arrays includes a set of macro-pixels and a local periphery circuit next to the set of macro-pixels. The local periphery circuit includes, for example, a buffer, a repeater, a clock gating circuit for gating an input clock signal to the sub-array, and/or a sub-array decoder for selecting the sub-array.

A current control circuit for LED or OLED sub-pixels or pixels of an active matrix display is able to store bits or a bit of a control signal used to drive a pixel or sub-pixel, in a memory associated with each pixel or sub-pixel. The control circuit elements can be made compatible with thin-film processing such as to produce thin-film transistors.

A display device includes a display panel configured to display an image, a data driver configured to supply a data voltage to the display panel, and a timing controller configured to control the data driver, and the data driver pauses a data latch operation.

An electroluminescent visual display unit having: a matrix of electroluminescent pixels formed from pixels arranged on a substrate, in a matrix arrangement in lines and columns, each pixel being formed by an elementary emitting zone; a first control block to control a graphic and/or alphanumeric data stream that can be displayed on the matrix of pixels; a second control block to control a video data stream that can be displayed on the matrix of pixels; and a unit for generating a reference voltage, the device being characterized in that: each elementary emitting zone is connected to a static memory, addressed by the first control block, and to a dynamic memory, addressed by the second control block; the first and second control blocks for displaying data alternately or simultaneously on the same matrix of pixels.

The present application relates to light-emitting diode (LED) driver circuits, display devices, and display systems. An example LED driver circuit includes: a driver including a plurality of data channels; a controller electrically connected to the driver. The controller is configured to, in response to detecting that data in all the data channels is 0 in a predetermined time period, control all the data channels to be in a closed state. The predetermined time period is determined based on a duration of an external input signal input to the LED driver circuit.

A power management integrated circuit includes a flip-flop circuit configured to perform a logic operation on a start clock signal which sets a driving start time point of a gate driving circuit and an on-clock signal which sets an output start time point of the gate driving circuit; a first AND gate circuit configured to receive one among output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate start signal; and a second AND gate circuit configured to receive the other of the output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate reset signal.

According to one embodiment, a display device includes a display area where a plurality of pixels are arrayed, a first drive circuit arranged adjacent to the display area in a first direction, the first drive circuit configured to supply a drive signal to a gate electrode included in each of switching elements, and a memory power line extending in a second direction intersecting the first direction in the display area and configured to supply a potential to a memories. An outer edge of the display area is defined by outermost edges of the pixels located on an outermost side in the display area. A first distance from the first drive circuit to the outer edge is shorter than a second distance from the first drive circuit to the memory power line.

Discussed is a display device including a substrate, semiconductor light-emitting elements on the substrate, flip-flops which can apply an electrical signal to the semiconductor light-emitting elements to maintain the semiconductor light-emitting elements in a light-emitting state for a predetermined time interval, scan electrodes and data electrodes electrically connected to the flip-flops, respectively, and a driver. When a frame synchronization signal is generated during a time interval from a time point of the generation of a sub field signal to a time point of the generation of a subsequent sub field signal, the driver can prevent a voltage from being applied to the data electrodes for the time interval.

An electronic display may include a pixel circuit. The pixel circuit may include memory storage to store data values representative of image data to be depicted via the pixel circuit. The memory storage may also include memory components for storing bits of the data value. The pixel circuit may also include a light-emitting device for emitting light based at least in part on the data value and a controller. The controller may receive the data value and store the bits based on a mapping between the bits and the memory components. The mapping may be determined based on routing one or more of the bits associated with one or more defective memory components of the memory components to one or more other memory components of the memory components. The controller may also drive the light-emitting device to emit light based on the bits stored in accordance with the mapping.