A display device includes a display panel including scan lines, first signal lines connected to the scan lines in a first pixel block, second signal lines connected to the scan lines in a second pixel block, third signal lines connected to the scan lines in a third pixel block; a first scan driver supplying a first output signal to the first signal lines based on a first sub-clock signal; a second scan driver supplying a second output signal to the second signal lines based on a second sub-clock signal; a third scan driver supplying a third output signal to the third signal lines based on and a third sub-clock signal; and a timing controller. Changes in pulse widths of the first to third output signals are different in one frame period.

A display apparatus may comprise: a panel driving unit comprising driving circuitry, a display panel, and a processor configured to control the panel driving unit, wherein the processor is configured to: control the panel driving unit to output gate signals to multiple gate lines sequentially one by one to process image data at a first driving frequency in a first mode, and control the panel driving unit to output gate signals to the multiple gate lines sequentially at least two gate lines at a time to process image data at a second driving frequency higher than the first driving frequency in a second mode.

According to an exemplary embodiment, an organic light emitting diode display includes: a substrate; a semiconductor layer; a first gate insulating layer disposed on the oxide semiconductor layer; a first gate layer disposed on the first gate insulating layer; a first interlayer insulating layer disposed on the first gate layer; a first data layer disposed on the first interlayer insulating layer; a second interlayer insulating layer disposed on the first data layer; a driving voltage line and a driving low voltage line disposed on the second interlayer insulating layer and separated from each other; an upper insulating layer covering the driving voltage line and the driving low voltage line; and an anode disposed on the upper insulating layer and overlapping the driving voltage line or the driving low voltage line.

A pixel circuit, a driving method and a display panel are provided by the disclosure. The pixel circuit includes: a sharing unit and N light-emitting control units. An input terminal of each of the light-emitting control units is electrically connected to an output terminal of the sharing unit; an output terminal of each of the light-emitting control units is electrically connected to a light-emitting element, a control terminal of each of the light-emitting control units is electrically connected a control signal line. The sharing unit is configured to drive, through each of the light-emitting control units. The light-emitting element electrically connected to the light-emitting control unit. N is positive integer greater than or equal to 2. The pixel circuit, the driving method and the display panel of the disclosure may solve the problem of the non-uniform display due to the drift of the threshold voltage of the driving transistor.

Provided are a display panel including a scan driver and a method of operating the same. The display panel includes a shift register including a plurality of stages that shifts and outputs a clock signal. A display area in the display panel is divided into a plurality of driving areas. The stages of the shift register corresponding to each driving area form a stage group. In each stage group, the stages included in the stage group sequentially output a scan signal by using an independent start signal.

A gate driving unit includes an input circuit, a pull-up circuit, a reset circuit, and an output circuit. The pull-up driving signals received by the input circuit include the gate driving signals for pixel units of row n−2 and row n+4. The reset driving signals received by the reset circuit include the gate driving signals for pixel units of row n+2 and row n+8. The gate driving signals output from the output circuit include the gate driving signals for pixel units of row n and row n+6. Where, n is a positive integer and nε[3,∞). The gate driving unit can output gate driving signals of two rows of pixel units and thus has a high service efficiency. An area occupied by a gate driving circuit made of the gate driving units is reduced, and a driving efficiency of the gate driving circuit is increased.

Proposed is a gate driver and a display device having the same. The gate driver includes a plurality of stage circuits, wherein each of the plurality of stage circuits includes a shift register configured to control charging and discharging of a Q node and a QB node, and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers includes a first transistor configured to transmit a voltage of the Q node to a Q′ node, a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node, and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.

A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

The present disclosure relates to the field of display technologies, and in particular, to a shift register circuit and a display device. The shift register circuit may include a plurality of GOAs for outputting scan signals to a plurality of pixel driving circuits and a plurality of EOAs for outputting control signals to the plurality of pixel driving circuits, where the GOAs and the EOAs are alternately arranged in a straight line.

Disclosed are a display driving circuit and a display apparatus including the same. A display driving circuit includes a first amplifier configured to drive a first data line of a display panel based on first pixel data and a second amplifier configured to drive a second data line of the display panel based on second pixel data, wherein, when a first data difference between the first pixel data and the second pixel data is greater than or equal to a data value indicating one grayscale and is less than or equal to a first threshold value, the second amplifier is turned off, and the first amplifier is configured to drive the first data line and the second data line based on the first pixel data and the second pixel data.