Proposed is a gate driver and a display device having the same. The gate driver includes a plurality of stage circuits, wherein each of the plurality of stage circuits includes a shift register configured to control charging and discharging of a Q node and a QB node, and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers includes a first transistor configured to transmit a voltage of the Q node to a Q′ node, a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node, and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.

A display device includes a plurality of pixels connected to a plurality of first scan lines, a plurality of second scan lines, and a plurality of data lines, where the pixels are arranged in a plurality of rows, a plurality of first stages connected to the first scan lines, a plurality of second stages connected to the second scan lines, and a data driver connected to the data lines. Each of the first scan lines is connected to pixels arranged in a corresponding row among the rows. Each of the second scan lines is commonly connected to pixels arranged in corresponding 8h rows among the plurality of rows, where h is a natural number.

An electronic device with short frame time length is provided. The electronic device includes a substrate, a plurality of first signal lines, a plurality of second signal lines, and two first integrated circuits. The plurality of first signal lines are disposed on the substrate. The plurality of first signal lines are divided into a first group of signal lines and a second group of signal lines. The plurality of second signal lines are disposed on the substrate. The plurality of second signal lines are disposed alternately with the plurality of first signal lines. The two first integrated circuits are bonded on the substrate. Each of the two first integrated circuits are electrically connected to the first group of signal lines and the second group of signal lines. The first group of signal lines and the second group of signal lines are disposed alternately in columns.

Provided are a display panel and a driving method. The display panel includes a pixel driving circuit including a drive transistor, a data write module, a light emission control module, a threshold compensation module and a bias adjustment module. The control terminal of the drive transistor is connected to the first node. The first terminal of the drive transistor is connected to a third node. The second terminal of the drive transistor is connected to a second node. The light emission control module is connected in series with the drive transistor and connected in series with a light-emitting element. The threshold compensation module is connected in series between the control terminal of the drive transistor and the second terminal of the drive transistor. The first terminal of the bias adjustment module is connected to a bias signal terminal. The second terminal is connected to the second terminal of the drive transistor.

Provided are a pixel driving circuit, a display panel and a driving method. The pixel driving circuit includes a drive transistor, a data write module, a light emission control module, a threshold compensation module and a bias adjustment module. The control terminal of the drive transistor is connected to the first node. The first terminal of the drive transistor is connected to a third node. The second terminal of the drive transistor is connected to a second node. The light emission control module is connected in series with the drive transistor and connected in series with a light-emitting element. The threshold compensation module is connected in series between the control terminal of the drive transistor and the second terminal of the drive transistor. The first terminal of the bias adjustment module is connected to a bias signal terminal. The second terminal of the bias adjustment module is connected to the second terminal of the drive transistor.

Disclosed herein are a gate driving circuit and a flexible display using the same. In gate driving circuit, a control block including an n.sup.th controller configured to generate one among a gate-off voltage, an EM start signal, and a carry signal from a (n-1).sup.th EM signal transfer part as an n.sup.th EM output control signal to apply the n.sup.th EM output control signal to a start terminal of an n.sup.th EM signal transfer part on the basis of an n.sup.th scan signal (n is a natural number) from the first shift register, a first control signal designating an off-driving signal transfer parts and an on-driving signal transfer parts among the EM signal transfer parts, a second control signal designating a first on-driving signal transfer part, and a third control signal designating second to last on-driving signal transfer parts.

A display device comprising: a first pixel row including a first pixel electrode and a second pixel electrode arranged in a first direction; a second pixel row including a third pixel electrode and a fourth pixel electrode arranged in the first direction; a third pixel row including a fifth pixel electrode and a sixth pixel electrode arranged in the first direction; a first source line and a second source line extending in the second direction between the first pixel electrode and the second pixel electrode; a first gate line extending in the first direction between the first pixel row and the second pixel row; a second gate line extending in the first direction between the second pixel row and the third pixel row; and a gate lead line extending in the second direction and connected to the first gate line and the second gate line.

A display device includes a display panel including scan lines, first signal lines connected to the scan lines in a first pixel block, second signal lines connected to the scan lines in a second pixel block, third signal lines connected to the scan lines in a third pixel block; a first scan driver supplying a first output signal to the first signal lines based on a first sub-clock signal; a second scan driver supplying a second output signal to the second signal lines based on a second sub-clock signal; a third scan driver supplying a third output signal to the third signal lines based on and a third sub-clock signal; and a timing controller. Changes in pulse widths of the first to third output signals are different in one frame period.

The present disclosure discloses a shift register, a gate line driving method, an array substrate, and a display apparatus, and belongs to the field of displays. The shift register comprises a plurality of shift register units each connected to a group of gate lines on an array substrate, wherein different shift register units are connected to different groups of gate lines, and each group of gate lines comprises at least two gate lines; and a control unit configured to control turn-on and turn-off of the gate lines, wherein the control unit is further configured to control various gate lines in a high resolution region to be turned on and turned off line by line, and control at least two adjacent gate lines in a low resolution region to be turned on and turned off synchronously.

Disclosed herein are a gate driving circuit and a flexible display using the same. In gate driving circuit, a control block including an n.sup.th controller configured to generate one among a gate-off voltage, an EM start signal, and a carry signal from a (n−1).sup.th EM signal transfer part as an n.sup.th EM output control signal to apply the n.sup.th EM output control signal to a start terminal of an n.sup.th EM signal transfer part on the basis of an n.sup.th scan signal (n is a natural number) from the first shift register, a first control signal designating an off-driving signal transfer parts and an on-driving signal transfer parts among the EM signal transfer parts, a second control signal designating a first on-driving signal transfer part, and a third control signal designating second to last on-driving signal transfer parts.