A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.

Mechanisms are provided to receive encoded header information stored on a tape of a tape drive, wherein the encoded header information has been generated by: generating, for a plurality of tracks of the tape of the tape drive, a header information in a plurality of symbols, wherein the plurality of symbols is comprised of a first set of symbols and a second set of symbols, wherein the first set of symbols include identical information across all tracks of the plurality of tracks, and wherein the second set of symbols are configurable to include different information across all tracks of the plurality of tracks; and modifying, for writing to the tape of the tape drive, the first set of symbols of the plurality of tracks to include parity information corresponding to information included in the second set of symbols of the plurality of tracks. The received encoded header information is decoded.

A system includes, according to one embodiment, a magnetic head having a plurality of write transducers configured to store data to tracks of a sequential access medium and a plurality of read transducers. Each read transducer is configured to read data from the sequential access medium after being written thereto by a corresponding write transducer. A first of the read transducers is aligned with a first of the write transducers, wherein the output of the first read transducer is produced during read-while-write. The system also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously. The logic is configured to determine that one or more tracks of the sequential access medium are dead within a sliding window and rewrite a set of encoded data from the one or more dead tracks to one or more live tracks in a rewrite area of the sequential access medium. Other systems, methods, and computer program products are described according to more embodiments.

In one embodiment, a system includes a magnetic head having a plurality of write transducers and a plurality of read transducers. Each read transducer is configured to read data from a sequential access medium after being written thereto by a corresponding write transducer. The system also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously. The logic is also configured to determine that one or more tracks of the sequential access medium are dead within a sliding window. Moreover, the logic is configured to rewrite a set of encoded data from the one or more dead tracks to live tracks in a rewrite area of the sequential access medium. Other systems, methods, and computer program products are described according to more embodiments.

In one embodiment, a system includes a magnetic head having a plurality of write transducers and a plurality of read transducers. Each read transducer is configured to read data from a sequential access medium after being written thereto by a corresponding write transducer. The system also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously. The logic is also configured to determine that one or more tracks of the sequential access medium are dead within a sliding window. Moreover, the logic is configured to rewrite a set of encoded data from the one or more dead tracks to live tracks in a rewrite area of the sequential access medium. Other systems, methods, and computer program products are described according to more embodiments.

A method, system, and non-transitory computer-readable recording medium of decoding a signal are provided. The method includes receiving signal to be decoded, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) and a path metric are determined for each possible path for each at least one bit at each stage; determining magnitudes of the LLRs; identifying K bits of the signal with smallest corresponding LLR magnitudes; identifying, for each of the K bits, L possible paths with largest path metrics at each decoder stage for a user-definable number of decoder stages; performing forward and backward traces, for each of the L possible paths, to determine candidate codewords; performing a Cyclic Redundancy Check (CRC) on the candidate codewords; and stopping after a first candidate codeword passes the CRC.

Method for decoding signal includes receiving signal, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) for each at least one bit at each stage is determined, and identified in vector L.sub.APP; performing Cyclic Redundancy Check (CRC) on L.sub.APP, and stopping if L.sub.APP passes CRC; otherwise, determining magnitudes of LLRs in L.sub.APP; identifying K LLRs in L.sub.APP with smallest magnitudes and indexing K LLRs as r={r(1), r(2), . . . , r(K)}; setting L.sub.max to maximum magnitude of LLRs in L.sub.APP or maximum possible LLR quantization value; setting v=1; generating {tilde over (L)}.sub.A(r(k))=L.sub.A(r(k))L.sub.maxv.sub.ksign[L.sub.APP(r(k))], for k=1, 2, . . . , K; decoding with {tilde over (L)}.sub.A to identify {tilde over (L)}.sub.APP, wherein {tilde over (L)}.sub.APP is LLR vector; and performing CRC on {tilde over (L)}.sub.APP, and stopping if {tilde over (L)}.sub.APP passes CRC or v=2.sup.K-1; otherwise, incrementing v and returning to generating {tilde over (L)}.sub.A(r(k)).

A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.

A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.

A method and system for decoding a signal are provided. The method includes receiving a signal, where the signal includes at least one symbol; decoding the signal in stages, where each at least one symbol is decoded into at least one bit per stage, wherein a Log-Likelihood Ratio (LLR) and a path metric are determined for each possible path for each at least one bit at each stage; determining the magnitudes of the LLRs; identifying K bits of the signal with the smallest corresponding LLR magnitudes; identifying, for each of the K bits, L possible paths with the largest path metrics at each decoder stage for a user-definable number of decoder stages; performing forward and backward traces, for each of the L possible paths, to determine candidate codewords; performing a Cyclic Redundancy Check (CRC) on the candidate codewords, and stopping after a first candidate codeword passes the CRC.