A memory and a read and write method of memory can prevent the magnetic random-access memory (MRAM) from being easily damaged or degraded by excessive write current during use, and increase memory integration density. The memory includes: a storage unit, comprising a storage element; a source line, electrically connected to a first end of the storage element; the memory is configured to change a storage state of the storage element by a first current and a second current, the first current flowing through the storage element and the second current flowing through the source line without flowing through the storage element.

A method for operating a differential memory includes: operating a main memory module differentially while executing a first program; copying first logic data from a first submodule of the main memory module to an auxiliary memory module; storing third logic data associated with a second program in a second submodule of the main memory module by overwriting second logic data associated with the first program, while maintaining the first logic data contained in the first submodule of the main memory module unaltered, where the second logic data are complementary to the first logic data; when a request for reading the first logic data is received during the storing of the third logic data in the second submodule of the main memory module, reading the first logic data from the auxiliary memory module; and executing the first or second programs by operating the main memory module in single-ended mode.

A semiconductor memory device includes a memory cell including a switching element and a resistance change element. A first circuit supplies a constant current to the memory cell for an amount of time and a second circuit applies a constant voltage to the memory cell for an amount of time. The semiconductor memory device places the memory cell into an ON state by applying, while applying a first current to the memory cell by the first circuit, a first voltage to the memory cell by the second circuit and performs readout on the memory cell in the ON state by the first current.

A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.

A voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction (MTJ) device includes a bottom electrode, a bottom CoFeB fixed layer disposed above and in electrical communication with the bottom electrode, a MgO layer disposed above the bottom CoFeB fixed layer, a top CoFeB free layer disposed above the MgO layer, a Mo capping layer disposed above the top CoFeB free layer, and a top electrode disposed above and in electrical communication with the Mo capping layer. A magnetization state of the top CoFeB free layer is switchable between an original state and an opposite state by applying a switching voltage across the MTJ device for a switching duration corresponding to a half period of a magnetic moment precession of the top CoFeB free layer.

In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal.

Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

The present disclosure provides a memory array, a memory cell, and a data read and write method thereof. Two storage nodes are provided in each memory cell of a memory array of a magnetic random access memory (MRAM), such that when one storage node in the memory cell fails, the other storage node in the memory cell can be used to write and read data.

A method of controlling a memory device can include: determining, by the memory device, a time duration in which the memory device is in a standby mode; automatically switching the memory device from the standby mode to a power down mode in response to the time duration exceeding a predetermined duration; exiting from the power down mode in response to signaling from a host device via an interface; and toggling a data strobe when data is ready to be output from the memory device in response to a read command from the host device.