An electronic device includes: a magnetic first nonvolatile memory that has no movable element; a nonmagnetic second nonvolatile memory; and a processor. The processor is configured to execute processing including: stopping writing data onto the first nonvolatile memory but writing the data onto the second nonvolatile memory in response to determining, based on magnetic field information regarding a magnetic field around the electronic device, that the electronic device is on a magnetic field equal to or stronger than a reference magnetic field strength in writing the data onto the first nonvolatile memory; and writing the data of the second nonvolatile memory onto the first nonvolatile memory in response to determining, based on the magnetic field information, that the electronic device is not on the magnetic field and that the data is on the second nonvolatile memory.

Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

A sensing circuit for detecting hardware trojans in a target integrated circuit is provided. The sensing circuit includes an array of magnetic tunnel junction circuits where each magnetic tunnel junction circuit including one or more magnetic tunnel junctions. Characteristically, each magnetic tunnel junction circuit configured to provide data for and/or determine a temperature map or a current map of the target integrated circuit.

An apparatus includes a perpendicular magnetic tunnel junction (MTJ) including a free layer. The apparatus includes a spin orbit torque metal layer coupled to the perpendicular MTJ and configured to change a magnetization state of the free layer responsive to flow of a current along the spin orbit torque metal layer. The apparatus includes a random number generator configured to generate a random number at least partially based on a state of the perpendicular MTJ.

Magnetic random access memory (MRAM)-based frame buffering apparatus are provided that may reduce a size and power consumption thereof by using a pixel self-refresh (PSR) method. The MRAM-based frame buffering apparatus includes a frame buffer memory including magnetic random access memory (MRAM). The frame buffer memory stores at least one piece of frame data. The MRAM-based frame buffering apparatus further includes a magnetic field sensor configured to detect an external magnetic field; and a frame buffer controller configured to control the storing of the at least one piece of frame data according to the intensity of the detected external magnetic field.

A peak current bypass protection control device applicable in MRAM is provided. In a memory unit array formed of a plurality of magnetic memory bit cells, each column of magnetic memory bit cells is connected in parallel with a bypass unit. When the magnetic memory bit cells of the memory unit array are being read/written, at the moment of switching on a switch, the bypass unit connected in parallel to the magnetic memory bit cells allows an instantaneous peak current to be guided out and prevents it from flowing through the magnetic memory bit cells.

According to one embodiment, a memory device includes a memory cell array; a generation circuit generating a reference current; a sense amplifier comparing a cell current flowing through a memory cell with the reference current; a first clamp transistor connected between the sense amplifier and the memory cell; a second clamp transistor connected between the sense amplifier and the generation circuit; a first interconnect layer connected to a gate of the first clamp transistor; a second interconnect layer connected to a gate of the second clamp transistor and arranged adjacent to the first interconnect layer; and a first shield line arranged adjacent to one of the first interconnect layer and the second interconnect layer, a fixed voltage being applied to the first shield line.

A magnetic memory includes: a magnetoresistance element; a conductive portion that is laminated on the magnetoresistance element; and a control portion configured to determine a driving temperature of the magnetoresistance element based on a change in a resistance value of the conductive portion and to control the amount of current applied to the magnetoresistance element.

Provided is a magnetic memory device. The magnetic memory device may include a magnetic tunnel junction. The magnetic tunnel junction may include a fixed layer, a tunnel barrier layer on the fixed layer, a free layer on the tunnel barrier layer, a protection layer above the free layer, the protection layer comprising an amorphous metal boride, and a capping layer on the protection layer, the capping layer comprising a metal or a metal nitride.

Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.