An ECU includes a RAM; a non-volatile memory; and a controller for controlling reading of data from, and writing of data into, the RAM and non-volatile memory. The controller is configured to: store data generated during operation into the RAM, write the data into a storage area of the non-volatile memory when the operation stops, and read the data from the non-volatile memory into the RAM when the operation starts, and control a control target using the data. When determining that an improper reset is expected, the controller writes at least part of the data generated during the operation and stored in the RAM into a save area, different from the data storage area, of the non-volatile memory. When the operation restarts from the improper reset, the controller reads, into the RAM, the data that has been written in the storage and save areas.

Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a wafer, multiple transistors, and a magnetoresistive random access memory (MRAM) cell disposed on the backside of the wafer. The transistors are disposed on a front end of line (FEOL) of the wafer. The MRAM cell is connected to a source-drain of the transistors by a contact disposed on the backside of the wafer. The transistors are in direct electrical contact with the MRAM cell by at least one contact.

The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.

A memory system includes a non-volatile memory and a memory controller configured to receive a command including an access target in the non-volatile memory and setting information from an external device and configured to control a writing operation or a reading operation to the access target. The memory controller has a condition setting circuit. The condition setting circuit is capable of performing the writing operation or the reading operation under a plurality of different conditions. The memory controller performs the writing operation or the reading operation under one of the plurality of different conditions selected by the condition setting circuit in accordance with the setting information.

A bias voltage generator includes a first current path, a first voltage clamp device, and a first buffer. The bias voltage generator receives a reference voltage and generates a first bias voltage based on a voltage difference between the reference voltage and a first drive voltage, the first voltage clamp device generates the first drive voltage based on the first bias voltage by applying the first drive voltage to the first current path, and the first buffer receives the first bias voltage and generates a second bias voltage based on the first bias voltage. A second current path includes a resistance-based memory device, and a second voltage clamp device generates a second drive voltage based on the second bias voltage and applies the second drive voltage to the second current path.

A power regulation system including a reference generator, a temperature compensation circuit coupled to the reference generator, and a low-dropout (LDO) regulator circuit coupled to the temperature compensation circuit, wherein the temperature compensation circuit provides a reference voltage to the LDO regulator circuit at least based on a ratio of a first current and a second current.

A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

A logic-memory cell includes a spin-orbit torque device having first, second and third terminals configured such that current between the second and third terminals is capable of changing a resistance between the first and second terminals. In the cell, a first transistor is connected between a logic connection line and the first terminal of the spin-orbit torque device and a second transistor is connected between the logic connection line and the third terminal of the spin-orbit torque device.

Multi-period thin-film structures exhibiting giant magnetoresistance (GMR) are described. Techniques are also described by which narrow spacing and/or feature size may be achieved for such structures and other thin-film structures having an arbitrary number of periods.

A packaged integrated circuit includes a photodiode and a memory. The photodiode generates energy when radiation strikes a surface of the photodiode. The memory includes a plurality of non-volatile memory cells and memory control circuitry. The memory control circuitry is configured to perform an operation to change values stored in at least some of the memory cells of the plurality of non-volatile memory cells while being powered by energy generated by the photodiode. An encapsulant at least partially encapsulates the photodiode and the memory, in which the encapsulant blocks radiation from reaching the surface of the photodiode.