A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell. The reference voltage generator is configured to generate a reference voltage based on a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage, and the reference voltage generator comprises a resistor that is configured to sense the threshold voltage of the select transistor through a current flowing through the resistor.

Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

A semiconductor circuit according to the present disclosure includes a first circuit that generates an inverted voltage of a voltage at a first node, and applies the inverted voltage to a second nodes, a second circuit that generates an inverted voltage of a voltage at the second node, and applies the inverted voltage to the first node, a first memory element that has a first terminal, a second terminal, and a third terminal, and stores information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state in accordance with a direction of a first current flowing between the first terminal and the second terminal, a first transistor that couples the first node to the third terminal of the first memory element and a second transistor that is coupled to a first coupling node.

A semiconductor circuit according to the present disclosure includes: a first circuit configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit configured to apply an inverted voltage of a voltage at a second node to the first node; a first storage element including first, second, and third terminals; a first transistor including a drain coupled to the first node and a source coupled to the first terminal of the first storage element; a second transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element; and a third transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element. The first storage element is configured to set a resistance state between the first terminal and the second and third terminals in accordance with a direction of a current flowing between the second and third terminals.

This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

A spin current magnetization rotational element according to the present disclosure includes a first ferromagnetic metal layer configured for a direction of magnetization to be changed and a spin-orbit torque wiring extending in a direction intersecting a lamination direction of the first ferromagnetic metal layer and bonded to the first ferromagnetic metal layer. The spin-orbit torque wiring includes a narrow portion, and at least a part of the narrow portion constitutes a junction to the first ferromagnetic metal layer.

A spin current magnetization rotational element according to the present disclosure includes a first ferromagnetic metal layer configured for a direction of magnetization to be changed and a spin-orbit torque wiring extending in a direction intersecting a lamination direction of the first ferromagnetic metal layer and bonded to the first ferromagnetic metal layer. The spin-orbit torque wiring includes a narrow portion, and at least a part of the narrow portion constitutes a junction to the first ferromagnetic metal layer.

A random code generator includes a differential cell array, a power supply circuit, a first selecting circuit and a current judgment circuit. The power supply circuit receives an enrolling signal and a feedback signal. The first selecting circuit receives a first selecting signal. When the enrolling signal is activated and an enrollment is performed on the first differential cell, the power supply circuit provides an enrolling voltage, and the enrolling voltage is transmitted to a first storage element and a second storage element of the first differential cell through the first selecting circuit. Consequently, the cell current is generated. When a magnitude of the cell current is higher than a specified current value, the current judgment circuit activates the feedback signal, so that the power supply circuit stops providing the enrolling voltage.