A magnetic memory device includes a first electrode, a second electrode, and a layer stack located between the first electrode and the second electrode. The layer stack includes a reference layer, a tunnel barrier layer, a free layer, and a magnetoelectric multiferroic layer including at least one crystalline grain. The magnetization of the magnetoelectric multiferroic layer may be axial, canted, or in-plane. For axial or canted magnetization of the magnetoelectric multiferroic layer, a deterministic switching of the free layer may be achieved through coupling with the axial component of magnetization of the magnetoelectric multiferroic layer. Alternatively, the in-plane magnetization of the magnetoelectric multiferroic layer may be employed to induce precession of the magnetization angle of the free layer.

A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.

A memory includes an array of resistive memory cells and circuitry for setting a write parameter for improving write effectiveness to the cells of the memory array. The circuitry performs a write parameter setting routine that determines a midpoint resistance of a memory state of cells of the array and determines a write efficiency of a weak write operation to cells of the array. Based on the determined midpoint resistance and the determined write efficiency, the circuit sets a write parameter level for subsequent writes to cells of the array.

Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.

The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

System and methods for implementing a multiply and accumulate (MAC) operation are described. In an example, a device can multiply an input digital signal with an input current to generate a current signal. The device can further divide the current signal into a plurality of currents. The device can further sample the plurality of currents sequentially using the same clock frequency. The device can further combine the plurality of sampled currents to generate an output current signal.

As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.

The disclosure provides a circuit structure and method for memory storage using a memory cell and magnetic random access memory (MRAM) stack. A circuit structure includes a memory cell having a first latch configured to store a digital bit, a first diode coupled to the first latch, and a first magnetic random access memory (MRAM) stack coupled to the first latch of the memory cell through the first diode. The first MRAM stack includes a first layer and a second layer each having a respective magnetic moment. The magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the first layer. Further, the magnetic anisotropy of the second layer can be modified through application of an applied voltage (VCMA effect). A spin Hall electrode is directly coupled to the first MRAM stack.

A semiconductor circuit according to the present disclosure includes: a first circuit that generates an inverted voltage of a voltage at a first node, and applies the inverted voltage to a second node; a second circuit that generates an inverted voltage of a voltage at the second node, and applies the inverted voltage to the first node; a first memory element that has a first terminal, a second terminal, and a third terminal, and stores information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state in accordance with a direction of a first current flowing between the first terminal and the second terminal; a first transistor that couples the first node to the third terminal of the first memory element by being turned on; and a second transistor that is coupled to a first coupling node being one of the first node and the second node, and causes the first current to flow to the second terminal of the first memory element on the basis of a voltage at the first coupling node.

Read circuitry for a memory cell of a resistive change memory is suggested, wherein a signal of a bit-line that is connected to the memory cell is compared with a reference signal, and wherein the reference signal is determined based on a first dummy circuit that determines a leakage current of memory cells addressed by the bit-line. Also, a corresponding method is provided.