A high speed, low power method to control and switch the magnetization direction of a magnetic region in a magnetic device for memory cells using spin polarized electrical current. The magnetic device comprises a pinned magnetic layer, a reference magnetic layer with a fixed magnetization direction and a free magnetic layer with a changeable magnetization direction. The magnetic layers are separated by insulating non-magnetic layers. A current can be applied to the device to induce a torque that alters the magnetic state of the device so that it can act as a magnetic memory for writing information. The resistance, which depends on the magnetic state of the device, can be measured to read out the information stored in the device.

A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.

The present disclosure provides magnetic sensor system that includes a magnetic sensing device comprising a magnetic multi-turn sensor, and an initialization device for setting the magnetic multi-turn sensor in a known state ready for use. The initialization device is in the form of a substrate, such as a printed circuit board, comprising one or more wires. A strong electrical pulse is applied to the one or more wires, which thereby generate a magnetic field that is strong enough to cause the magnetoresistive elements of the magnetic multi-turn sensor to be filled with domain walls, thereby magnetising each element into an initialized state.

A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

According to one embodiment, a memory device includes a spin transfer torque magnetoresistive element including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, a temperature detecting unit detecting an ambient temperature of the magnetoresistive element, and a write voltage generating unit generating a write voltage for the magnetoresistive element in accordance with the temperature detected by the temperature detecting unit.

A magnetic memory device may include a bit line, a plurality of source lines, a plurality of normal cells coupled between the bit line and the plurality of source lines, and each including a magnetic resistance element and a switching element coupled in series to the magnetic resistance element and switched by a word line signal, a dummy cell coupled to the bit line, and a spin-hall effect material layer between the bit line and the magnetic resistance element. The magnetic resistance element may write data according to a first current that flows through the dummy cell and flows in a direction parallel to the magnetic resistance element, and a second current that flows through the magnetic resistance element.

A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.

A method for sensing logical states of memory cells in multiple segments in a memory device, each cell having a high- and low-resistance state, resulting in different cell current levels for the different resistance states. The method includes determining target reference current levels for the respective segments, at least two of the target reference current levels being different from each other; generating a reference current for each segment with the target reference current level for that segment; comparing the cell current level for each cell to the reference current level for the segment the cell is in; and determining the logical states of the memory cells based on the comparison.

A memory apparatus and a memory device are provided. The memory apparatus includes a memory device including a plurality of memory cells and a driving circuit configured to control the memory cells; wherein each of the memory cells includes a memory layer where a magnetization direction is changeable by a current, a magnetic fixed layer having a fixed magnetization, an intermediate layer including a non-magnetic material provided between the memory layer and the magnetic fixed layer, a top electrode provided over the memory layer, a bottom electrode provided over the magnetic fixed layer; wherein the current is configured to flow in a lamination direction between the top electrode and the bottom electrode.