A semiconductor device that writes data to, instead of a defective memory cell, another memory cell is provided. The semiconductor device includes a first circuit and a second circuit over the first circuit; the first circuit corresponds to a memory portion and includes a memory cell and a redundant memory cell; a second circuit corresponds to a control portion and includes a third circuit and a fourth circuit. The memory cell is electrically connected to the third circuit, the redundant memory cell is electrically connected to the third circuit, and the third circuit is electrically connected to the fourth circuit. The fourth circuit has a function of sending data to be written to the memory cell or the redundant memory cell to the third circuit, and the third circuit has a function of bringing the memory cell and the fourth circuit into a non-conduction state and the redundant memory cell and the fourth circuit into a conduction state to send the data to the redundant memory cell when the memory cell is a defective cell.

To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

This invention comprises a new way to connect a control, CK, and data, D, signal into a basic cross-coupled INV pair, and into certain other basic sequential logic circuits, to control the writing in of a new data value, D, into the sequential logic circuit cell. The invention concerns logic circuit in complementary metal-oxide-semiconductor (CMOS) technology. It connects additional p-type and n-type MOSFET devices in a novel manner to accomplish the desired control functions.

A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.

A compute-in-memory array is provided that includes a set of compute-in-memory bitcells that time share a shared capacitor connected between the set of compute-in-memory bitcells and a read bit line.

A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

A compiler receives a description of a machine learning network (MLN) and generates a computer program that implements the MLN on a machine learning accelerator (MLA). To implement the MLN, the compiler generates compute instructions that implement computations of the MLN on different processing units (Tiles), and data transfer instructions that transfer data used in the computations. The compiler may statically schedule at least a portion of the instructions for execution by the Tiles according to fixed timing. The compiler may initially implement data transfers between non-adjacent Tiles (or external memories) by implementing a sequence of transfers through one or more intermediate Tiles (or external memories) in accordance with a set of default routing rules that dictates the data path. The computer program may then be simulated to identify routing conflicts. When routing conflicts are detected, the compiler updates the computer program in a manner that avoids the conflicts.