A semiconductor memory device includes a memory block with string units including a plurality of memory strings of memory cell transistors connected in series. Word lines are connected memory cell transistors in a same row and bit lines are respectively connected to one of the memory strings in each string unit. The bit lines are divided into different groups. A control circuit performs erasing on of the memory cell transistors in the memory block. The control circuit executes the erase verification on only a subset of memory strings in each string unit of the memory block rather than all memory strings.

Provided herein are a nonvolatile memory device and a method of programming the same. The nonvolatile memory device includes a memory cell array including a plurality of word lines having a first word line and a plurality of memory cells connected to the first word line. The plurality of memory cells includes a plurality of monitoring cells and a plurality of data cells each data cell configured to store N-bit data, N being a natural number. The nonvolatile memory device is configured to perform a first program on the plurality of data cells and a detection program different from the first program on the one or more monitoring cells after performing the first program.

A method for programming a memory block of a non-volatile memory structure, wherein the method provides, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.

A method for programming a memory block of a non-volatile memory structure, comprising determining whether a number of programming/erase cycles previously applied to the block exceeds a first programming/erase cycle threshold and, if the first threshold is exceeded, determining whether the number of programming/erase cycles previously applied to the block exceeds an extended programming/erase cycle threshold. Further, if the determination is made that the extended threshold is not exceeded, the method comprises applying a two-pulse per programming loop scheme to each of the outermost strings of the block and applying a single-pulse per programming loop scheme to all other strings of the block. Alternatively, or in addition thereto, relative to a programming/erase cycle threshold, one or more outermost strings of the block may be unpermitted to be further programmed, and a “sub-block” comprised of all valid strings of the block may be defined and permitted for further programming.

Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.

A method for detecting a “slow to erase” condition of a non-volatile memory structure, wherein the method comprises initiating an erase/verify memory operation with respect to the memory structure, wherein the erase/verify memory operation comprises applying an erase verify voltage according to an alternating word line scheme; following the erase/verify memory operation, determining if a first bit scan mode criteria is satisfied; and, if the first bit scan mode criteria is satisfied, initiating a read/verify memory operation wherein, the read/verify memory operation comprises applying a read-pass voltage according to an all word line scheme, and a magnitude of the read-pass voltage is greater than a magnitude of the erase verify voltage. Following the read/verify memory operation, the method also comprises determining if a second bit scan mode criteria is satisfied and, if the criteria is not satisfied, designating the memory structure with a fail status.

Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.

A method for programming a memory block of a non-volatile memory structure, comprising determining whether a number of programming/erase cycles previously applied to the block exceeds a first programming/erase cycle threshold and, if the first threshold is exceeded, determining whether the number of programming/erase cycles previously applied to the block exceeds an extended programming/erase cycle threshold. Further, if the determination is made that the extended threshold is not exceeded, the method comprises applying a two-pulse per programming loop scheme to each of the outermost strings of the block and applying a single-pulse per programming loop scheme to all other strings of the block. Alternatively, or in addition thereto, relative to a programming/erase cycle threshold, one or more outermost strings of the block may be unpermitted to be further programmed, and a “sub-block” comprised of all valid strings of the block may be defined and permitted for further programming.

A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.

A request to perform a secure erase operation for a memory component can be received. A voltage level that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can be associated with a program operation to place a memory cell of the memory component at another voltage level that exceeds the voltage level that is applied to the unselected wordlines of the memory component during the read operation.