A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured to, if the at least one memory string passes the erase-verify test, inhibit the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string and to perform a next erase-verify iteration in the erase operation for remaining memory strings of the plurality of memory strings other than the at least one memory string.

Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.

A data writing and reading method is applied to a data storage system. The storage system includes a processor, a charged particle beam excitation modulation component, and a recording medium. The method is performed by the processor. The data writing method includes obtaining to-be-written data; controlling, based on the to-be-written data, the charged particle beam excitation modulation component to generate a charged particle beam array with a target modulation feature; and controlling the charged particle beams in the charged particle beam array to act on the recording medium to generate, in a target area of the recording medium, a target recording feature corresponding to the to-be-written data.

In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.

A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls the program operation of the peripheral circuit. The program operation includes a plurality of program loops. The control logic is configured to control the peripheral circuit to apply a program voltage to a select word line that is connected to the selected memory cells, apply a first under drive voltage that is determined based on at least one verify voltage to the select word line, and apply the at least one verify voltage to the select word line in each of the plurality of program loops. The first under drive voltage is at a lower voltage level than the at least one verify voltage.

To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

Disclosed approaches for validating initialization vectors determining by a configuration control circuit whether or not an input initialization vector is within a range of valid initialization vectors. In response to determining that the initialization vector is within the range of valid initialization vectors, the configuration control circuit decrypts the ciphertext into plaintext using the input initialization vector and configures a memory circuit with the plaintext. In response to determining that the first initialization vector is outside the range of valid initialization vectors, the configuration control circuit signals that the first initialization vector is invalid.

Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.

The present technology relates to an electronic device. A memory device having improved memory block management performance according to the present technology includes a memory block, a peripheral circuit, and a control logic. The peripheral circuit performs a read operation and a program operation on a selected physical page among a plurality of physical pages. The control logic controls the peripheral circuit to read first logical page data stored in a first physical page and second logical page data stored in a second physical page among the plurality of physical pages, and additionally program the second logical page data into the first physical page using the read first and second logical page data.