Patent classifications
G11C13/0026
Systems and methods for adaptive self-referenced reads of memory devices
Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.
Negative-capacitance ferroelectric transistor assisted resistive memory programming
A memory device is provided that includes at least one resistive memory cell, a negative capacitance field effect transistor (NC-FET) serving as a voltage amplifier, and a switch enable circuit connecting NC-FET to the memory cell. The NC-FET includes a regular FET having a metal gate terminal and a ferroelectric capacitor. The NC-FET gate terminal forms one plate of the ferroelectric (FE) capacitor. The ferroelectric capacitor includes a ferroelectric dielectric material deposited between a formed upper gate conductive contact and he metal gate terminal. To provide further flexibility, a metal layer can be deposited before the deposition of the ferroelectric material to form a MIM-like FE capacitor so that the capacitance of FE capacitance can be independently tuned by choosing the right height (H), width (W), and length (L) to achieve desired matching between |C.sub.FE| and C.sub.ox where C.sub.ox is the gate oxide capacitance and C.sub.FE is the ferroelectric capacitance.
BISPECIFIC BINDING MOLECULES THAT ARE CAPABLE OF BINDING CD137 AND TUMOR ANTIGENS, AND USES THEREOF
The present invention is directed to binding molecules that possess one or more epitope-binding sites specific for an epitope of CD137 and one or more epitope-binding sites specific for an epitope of a tumor antigen (“TA”) (e.g., a “CD137×TA Binding Molecule”). In one embodiment, such CD137×TA Binding Molecules will be bispecific molecules, especially bispecific tetravalent diabodies, that are composed of two, three, four or more than four polypeptide chains and possessing two epitope-binding sites each specific for an epitope of CD137 and two epitope-binding sites each specific for an epitope of a TA. Alternatively, such CD137×TA Binding Molecules will be bispecific molecules, especially bispecific trivalent binding molecules composed of three or more polypeptide chains and possessing one or two epitope-binding sites each specific for an epitope of CD137 and one or two epitope-binding sites each specific for an epitope of a TA. The CD137×TA Binding Molecules of the invention are capable of simultaneous binding to CD137, and a TA. The invention is directed to pharmaceutical compositions that contain any such CD137×TA Binding Molecules. The invention is additionally directed to methods for the use of such molecules in the treatment of cancer and other diseases and conditions. The invention also provides novel CD137-binding molecules, and HER2/neu-binding molecules, as well as derivatives thereof and uses thereof.
ACCESS TO A MEMORY
In a method for accessing memory cells, a first read operation is performed on a first memory cell to read a first data value from the first memory cell. During the first read operation, a first variable current source provides a first assessment current having a first current level to a first bitline coupled to the first memory cell. A second read operation is performed on the first memory cell to read a second data value from the first memory cell. During the second read operation, the first variable current source manipulates the first current level to provide a second current level to the first bitline. A difference between the first current level and the second current level is based on whether the first data value that was read during the first read operation was a first data state or a second data state.
RESISTIVE MEMORY WITH VERTICAL TRANSPORT TRANSISTOR
Embodiments of the present invention include a memory cell that has a vertically-oriented fin. The memory cell may also include a resistive memory device located on a first lateral side of the fin. The resistive memory device may include a bottom electrode, a top electrode, and a resistive element between the bottom electrode and the top electrode. The memory cell may also include a vertical field-effect transistor having a metal gate and a gate dielectric contacting a second lateral side of the fin opposite the first lateral side.
Automated method and associated device for the non-volatile storage, retrieval and management of message/label associations and vice versa, with maximum likelihood
An associative-memory-storage unit, and to an associative-memory-storage method are provided. The associative-memory-storage unit includes a first subset of at least memory sub-units over w bits, and a second memory sub-unit over v bits. The associative-memory-storage sub-unit may be used to associate messages with labels, and vice versa.
RRAM current limiting method
A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.
Voltage drivers with reduced power consumption during polarity transition
An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.
Self-Selecting Memory Cells Configured to Store More Than One Bit per Memory Cell
Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.
Programming Intermediate State to Store Data in Self-Selecting Memory Cells
Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.