Apparatuses and methods for sensing a resistance variable memory cell include circuitry to apply a programming signal to a memory cell in the array, the programming signal associated with programming resistance variable memory cells to a particular data state, and detect a change in resistance of the memory cell to determine if a data state of the memory cell changes from an initial data state to a different data state during application of the programming signal.

Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.

Apparatuses and methods for sensing a resistance variable memory cell include circuitry to apply a programming signal to a memory cell in the array, the programming signal associated with programming resistance variable memory cells to a particular data state, and detect a change in resistance of the memory cell to determine if a data state of the memory cell changes from an initial data state to a different data state during application of the programming signal.

A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (.sub.VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (V.sub.TH1) of the memory cell and determining whether the V.sub.TH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped V.sub.TH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (V.sub.TH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the V.sub.TH1 and the V.sub.TH2.

A memory device including: a memory cell array, including a memory cell having a switch element and a data storage element connected to the switch element, wherein the data storage element has a phase change material; and a memory controller for inputting a first read current to the memory cell to detect a first read voltage, inputting a second read current to the memory cell to detect a second read voltage, and inputting a compensation current to the memory cell, wherein the compensation current lowers a resistance value of the data storage element, the compensation current is input when a first state of the memory cell is different from a second state of the memory cell, the first state is determined using the first read voltage and the second state is determined using the second read voltage.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (.sub.VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (V.sub.TH1) of the memory cell and determining whether the V.sub.TH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped V.sub.TH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (V.sub.TH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the V.sub.TH1 and the V.sub.TH2.

Methods, apparatuses and systems related to reading data from memory cells configured to store more than one bit are described. The apparatus may be configured to determine a polarity data associated with reading data stored at a target location. In reading the data stored at the target location, the apparatus may apply one or more voltage levels across different polarities according to the determined polarity data.

A semiconductor memory device includes a resistive-type memory cell and a sense amplifier for reading data from the memory cell. First and second transistors connected in parallel between a first node connected to the memory cell and a second node connected to the sense amplifier. The first transistor has a size that is different from the second transistor. Each of the first and second transistors has a gate that is connected to a first voltage source. A switch circuit controls a conduction state between the first and second nodes via separate paths through the first transistor and the second transistor. The sense amplifier compares a first current supplied to the memory cell via the first path at a first timing and a second current supplied to the memory cell via the second path at a second timing different from the first timing.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (.sub.VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (V.sub.TH1) of the memory cell and determining whether the V.sub.TH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped V.sub.TH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (V.sub.TH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the V.sub.TH1 and the V.sub.TH2.