The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

A programmable non-volatile memory device effectuates two different functions (read, erase (re-program)) during a single instruction or command. During a first phase of the command a cell state is determined by a memory controller circuit, and in a second phase of the same command the cell state is re-written. This implementation is useful for applications where it is desirable to permit one time access only of particular data/content.

A semiconductor memory device includes a resistive-type memory cell and a sense amplifier for reading data from the memory cell. First and second transistors connected in parallel between a first node connected to the memory cell and a second node connected to the sense amplifier. The first transistor has a size that is different from the second transistor. Each of the first and second transistors has a gate that is connected to a first voltage source. A switch circuit controls a conduction state between the first and second nodes via separate paths through the first transistor and the second transistor. The sense amplifier compares a first current supplied to the memory cell via the first path at a first timing and a second current supplied to the memory cell via the second path at a second timing different from the first timing.

A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.

The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (.sub.VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (V.sub.TH1) of the memory cell and determining whether the V.sub.TH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped V.sub.TH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (V.sub.TH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the V.sub.TH1 and the V.sub.TH2.

To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device that has a memory having at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other.

An electronic device comprising a semiconductor memory unit that may a variable resistance element configured to be changed in its resistance value in response to current flowing through both ends thereof; an information storage unit configured to store switching frequency information corresponding to a switching frequency which minimizes an amplitude of a voltage to be applied to both ends of the variable resistance element to change the resistance value of the variable resistance element and switching amplitude information corresponding to a minimum amplitude; and a driving unit configured to generate a driving voltage with the switching frequency and the minimum amplitude in response to the switching frequency information and the switching amplitude information and apply the driving voltage to both ends of the variable resistance element.

A method for reading out a resistive memory cell comprising two electrodes that are spaced from each other by an ion-conducting resistive material was developed, the memory cells being transferrable from a stable state having a higher resistance value (high resistive state, HRS) to a stable state having a lower resistance value (low resistive state, LRS) when a write voltage is applied. A read voltage is applied as a read pulse for reading out, wherein the number of ions driven through the ion-conducting resistive material during the pulse is set by way of the level and duration of the pulse in such a way, proceeding from the HRS state, they suffice for forming an electrically conducting path through the ion-conducting resistive material at least until the onset of a flow of current through this path, and thus for the transition into a metastable VRS state (volatile resistance state) having a reduced resistance value and a predefined relaxation time for return into the HRS state, but not for transition into the LRS state. In this way, it is ensured that, in all cases, the memory cell once is again in the same state after the read-out as it was prior to the read-out. This allows in particular memory elements that are composed of an antiserial circuit composed of two memory cells to be read out non-destructively, without this diminishing the option of implementing large arrays composed of these memory elements.

Apparatuses and methods for sensing a resistance variable memory cell include circuitry to apply a programming signal to a memory cell in the array, the programming signal associated with programming resistance variable memory cells to a particular data state, and detect a change in resistance of the memory cell to determine if a data state of the memory cell changes from an initial data state to a different data state during application of the programming signal.