A semiconductor memory may include: a first variable resistance element including a first terminal and a second terminal; a second variable resistance element including a first terminal, a second terminal, and a third terminal; a first transistor configured to control an electrical connection between a first conductive line and the first terminal of the first variable resistance element; a second transistor configured to control an electrical connection between the first conductive line and the first terminal of the second variable resistance element; a connection layer structured to electrically connect the second terminal of the first variable resistance element to the second and third terminals of the second variable resistance element; and a third conductive line is electrically connected to the connection layer.

Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

A memory cell, includes first and second main terminals, an auxiliary terminal; M memristor(s) between the main terminals, M≥1; M primary switch(es), each in parallel with a memristor; and a secondary switch between the second main terminal and the auxiliary terminal. It is configured for writing to at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; and for reading at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other possible primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the main terminals.

An embodiment of the invention may include a memory structure. The memory structure may include a first terminal connected to a first contact. The memory structure may include a second terminal connected to a second contact and a third contact. The memory structure may include a multi-level nonvolatile electrochemical cell having a variable resistance channel and a programming gate. The memory structure may include the first contact and second contact connected to the variable resistance channel. The memory structure may include the third contact is connected to the programming gate. This may enable decoupled read-write operations of the device.

A memory cell includes a first electrode, a second electrode, a variable resistance layer located between the first electrode and the second electrode, and a ferroelectric layer located between the variable resistance layer and the second electrode, wherein the variable resistance layer is maintained in an amorphous state during a program operation.

The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. An embodiment includes a memory having a group of memory cells, and circuitry configured to, upon a quantity of sense operations performed on the group of memory cells meeting or exceeding a threshold quantity, perform a sense operation on the group of memory cells using a positive sensing voltage and perform a sense operation on the group of memory cells using a negative sensing voltage, and perform an operation to program the memory cells of the group determined to be in a reset data state by both of the sense operations to the reset data state.

A phase-change material based resistive memory contains a resistive layer and two electrical contacts. After fabrication the memory is subjected to thermal treatment which initiates a transition toward a crystalline state favoring in this way the subsequent obtaining of a large number of resistive memory states.

An operating circuit and an operating method of a resistive random-access memory are provided, the operating circuit includes: at least one capacitance connected in series with the resistive random-access memory, so that the resistive random-access memory is grounded through the at least one capacitance. The operating method includes: connecting at least one capacitance in series with a resistive random-access memory, so that the resistive random-access memory is grounded through the capacitance; applying a forming pulse voltage or a set pulse voltage on the resistive random-access memory to achieve a forming operation or a set operation of the resistive random-access memory.