An indication that an allocation unit of a memory sub-system has become unmapped can be received. In response to receiving the indication that the allocation unit of the memory sub-system has become unmapped, the allocation unit can be programmed with a data pattern. Data to be written to the unmapped allocation unit can be received. A write operation can be performed to program the received data at the unmapped allocation unit by using a read voltage that is based on the data pattern.

A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.

Methods, systems, and devices for cleaning memory blocks using multiple types of write operations are described. A counter may be incremented each time a write command is received. In response to the counter reaching a threshold, the counter may be reset and a flag may be set. Each time a cleaning of a memory block is to take place, the flag may be checked. If the flag is set, the memory block may be cleaned using a second type of cleaning operation, such as one using a force write approach. Otherwise, the memory block may be cleaned using a first type of cleaning operation, such as one using a normal write approach. Once set, the flag may be reset after one or more memory blocks are cleaned using the second type of cleaning operation.

A memory device has multiple nonvolatile (NV) memory arrays that collectively store a block of data, with each array to store a portion of the data block. A selected NV memory array stores a write count for the block of data. In response to a write command, the NV memory arrays that store data perform an internal pre-write read. The selected NV memory array that stores the write count will perform a pre-write read of the write count, increment the write count internally to the selected NV memory array, and write the incremented write count back to the selected NV memory array.

Methods and apparatus are disclosed for managing the storage of dynamic neural network data within bit-addressable memory devices, such phase change memory (PCM) arrays or other storage class memory (SCM) arrays. In some examples, a storage controller determines an expected amount of change within data to be updated. If the amount is below a threshold, an In-place Write is performed using bit-addressable writes via individual SET and RESET pulses. Otherwise, a modify version of an In-place Write is performed where a SET pulse is applied to preset a portion of memory to a SET state so that individual bit-addressable writes then may be performed using only RESET pulses to encode the updated data. In other examples, a storage controller separately manages static and dynamic neural network data by storing the static data in a NAND-based memory array and instead storing the dynamic data in a SCM array.

Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

An embodiment in the application may include an analog memory structure, and methods of writing to such a structure, including a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resistance upon application of a voltage. This may enable accelerated writing of the analog memory structure.

A non-volatile memory device includes a memory cell array, a word line driver, a bit line driver, a read circuit, and control logic. The memory cell array includes a plurality of banks. Each bank includes a plurality of tiles. Each tile includes a plurality of resistive memory cells connected to a plurality of bit lines and a plurality of word lines. The word line driver selects one of the word lines in response to an input address. The bit line driver selects one of the bit lines in response to the input address. The read circuit reads a code word from the memory cell array in a read operation. The control logic is configured to control the word line driver, the bit line driver, the read circuit in the read operation. The control logic performs an address scramble on the input address, and provides the scrambled address to the read circuit to access the plurality of tiles in the read operation.

An example non-transitory machine-readable storage medium storing machine-readable instructions which when executed cause a processor to obtain stored bits stored on a flash memory, each of the stored bits in a set state or an unset state. The processor further obtains target bits, each of the target bits in the set state or the unset state, wherein each target bit corresponds to a stored bit to update the stored bit. The processor further determines whether, for one stored bit in the set state, the corresponding target bit is in the unset state. When the determination is positive, the processor sets the stored bits to the unset state and, after setting the stored bits to the unset state, updates the stored bits to match the corresponding target bits. When the determination is negative, the processor updates the stored bits to match the corresponding target bits.

Systems, apparatuses, and methods related to image based media type selection are described. Memory systems can include multiple types of memory media. Data can be written in a type of memory media based on one or more settings applied to the data. A setting can be determined based on input received by a logic within the memory system. In an example, a method can include receiving, at logic within a memory system that comprising a plurality of memory media types, data from an image sensor coupled to the logic of the memory system, receiving input from a host, identifying one or more attributes of the data, analyzing the received input to determine an setting, generating the setting based on the analyzed input, and writing the data to a first memory media type of the plurality of memory media types based on the generated setting.