Patent classifications
G11C2013/008
PCRAM ANALOG PROGRAMMING BY A GRADUAL RESET COOLING STEP
In some embodiments, the present disclosure relates a phase change random access memory device that includes a phase change material (PCM) layer disposed between bottom and top electrodes. A controller circuit is coupled to the bottom and top electrodes and is configured to perform a first reset operation by applying a signal at a first amplitude across the PCM layer for a first time period and decreasing the signal from the first amplitude to a second amplitude for a second time period; and to perform a second reset operation by applying the signal at a third amplitude across the PCM layer for a third time period and decreasing the signal from the third amplitude to a fourth amplitude for a fourth time period greater than the second time period. After the fourth time period, the PCM layer has a percent crystallinity greater than the PCM layer after the second time period.
INTEGRATED CIRCUIT SECURITY USING PROGRAMMABLE SWITCHES
A security key associated with a plurality of programmable switches included in an integrated circuit is received. The plurality of programmable switches are set causing the plurality of programmable switches to be conductive. Reset pulses are applied to a first set of programmable switches included in the plurality of programmable switches based on the received security key.
PHASE-CHANGE MATERIAL-BASED XOR LOGIC GATES
An apparatus comprises a phase-change material, a first electrode at a first end of the phase-change material, a second electrode at a second end of the phase-change material, and a heating element coupled to a least a given portion of the phase-change material between the first end and the second end. The apparatus also comprises a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.
CHIP CONTAINING AN ONBOARD NON-VOLATILE MEMORY COMPRISING A PHASE-CHANGE MATERIAL
An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.
Memory cell comprising a phase-change material
A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
Controlling positive feedback in filamentary RRAM structures
A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.
Semiconductor logic circuits including a non-volatile memory cell
A phase change memory (PCM) device including a bottom electrode, a bottom heater over the bottom electrode, a bottom buffer layer over the bottom heater, a PCM region over the bottom buffer layer, a top buffer layer over the PCM region, a top heater over the top buffer layer, and a top electrode over the top heater.
PHASE-CHANGE MEMORY DEVICE HAVING REVERSED PHASE-CHANGE CHARACTERISTICS AND PHASE-CHANGE MEMORY HAVING HIGHLY INTEGRATED THREE-DIMENSIONAL ARCHITECTURE USING SAME
According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.
Resistive Element for PCM RPU by Trench Depth Patterning
Resistive elements for PCM RPUs and techniques for fabrication thereof using trench depth pattering are provided. In one aspect, an RPU device includes: a first electrode; a second electrode; a heater; and a PCM disposed over the first electrode, the second electrode and the heater, wherein the heater includes a combination of a first material having a resistivity r1 and a second material having a resistivity r2, wherein r1>r2, and wherein only the first material is present beneath the PCM and forms a resistive heating element. A method of operating an RPU device is also provided.
Memory cell
A phase-change memory cell is formed by a heater, a crystalline layer disposed above the heater, and an insulating region surrounding sidewalls of the crystalline layer. The phase-change memory cell supports programming with a least three distinct data levels based on a selective amorphization of the crystalline layer.