A resistance change device of an embodiment includes: a first electrode; a second electrode; and a stack disposed between these electrodes, and including a first layer containing a resistance change material and a second layer in contact with the first layer. The resistance change material contains at least one of a first element such as Ge and a second element such as Sb, and at least one third element selected from Te, Se, S, and O. The second layer contains a crystal material containing at least one selected from a group consisting of a first material having a composition represented by (Ti,Zr,Hf)CoSb, (Zr,Hf)NiSn, or Fe(Nb,Zr,Hf)(Sb,Sn), a second material having a composition represented by Fe(V,Hf,W)(Al,Si), and a third material having a composition represented by Mg(Si,Ge,Sn).

A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.

In some embodiments, the present disclosure relates a phase change random access memory device that includes a phase change material (PCM) layer disposed between bottom and top electrodes. A controller circuit is coupled to the bottom and top electrodes and is configured to perform a first reset operation by applying a signal at a first amplitude across the PCM layer for a first time period and decreasing the signal from the first amplitude to a second amplitude for a second time period; and to perform a second reset operation by applying the signal at a third amplitude across the PCM layer for a third time period and decreasing the signal from the third amplitude to a fourth amplitude for a fourth time period greater than the second time period. After the fourth time period, the PCM layer has a percent crystallinity greater than the PCM layer after the second time period.

A memory device includes a plurality of memory cells, each memory cell including a switching element and a data storage element having a phase change material, and each memory cell connected to one of a plurality of wordlines and to one of a plurality of bitlines, a decoder circuit configured to determine at least one of the plurality of memory cells as a selected memory cell, and a programming circuit configured to input a program current to the selected memory cell to perform a program operation, to detect a holding voltage of the selected memory cell, and to adjust a magnitude of the program current based on the detected holding voltage. The selected memory cell is turned off when a voltage across the selected memory cell is lower than the holding voltage.

A memory device includes a substrate; a bottom electrode disposed over the substrate; an insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer; a heater disposed in the through hole; a phase change material layer disposed over the heater; a selector layer disposed over the phase change material layer; and a metal layer disposed over the selector layer. The metal layer is wider than the phase change material layer.

Present disclosure provides a semiconductor structure and a method for fabricating a semiconductor device. The semiconductor includes a transistor, a first metallization layer over the transistor, a phase change material over the first metallization layer, a second metallization layer over the phase change material, a heater between the first metallization layer and the second metallization layer and in contact with the phase change material, the heater including a heat insulation shell having a first heat conductivity, wherein the heat insulation shell includes a superlattice structure, and a heat conducting core contacting the heat insulation shell and having a second heat conductivity different from the first heat conductivity.

Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

A reactive material erasure element comprising a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.

Phase-change memory cells and methods of manufacturing and operating phase-change memory cells are provided. In at least one embodiment, a phase-change memory cell includes a heater and a stack. The stack includes at least one germanium layer or a nitrogen doped germanium layer, and at least one layer of a first alloy including germanium, antimony, and tellurium. A resistive layer is located between the heater and the stack.

The present invention provides RRAM devices with tunable forming voltage. In one aspect, a method of forming an RRAM device includes: depositing a first dielectric layer on a substrate; forming metal pads in the first dielectric layer; depositing a capping layer onto the first dielectric layer; forming heating elements in the capping layer in contact with the metal pads; forming an RRAM stack on the capping layer; patterning the RRAM stack into an RRAM cell(s) including a bottom electrode, a high-κ switching layer disposed on the bottom electrode, and a top electrode disposed on the high-κ switching layer; depositing a second dielectric layer over the RRAM cell(s); and forming a contact to the top electrode in the second dielectric layer. An RRAM device and a method of operating an RRAM device are also provided.