A resistive memory device includes word lines, first memory cells, second memory cells, bit lines, source lines, and a driver. The driver provides a forming voltage to the first memory cells and the second memory cells through the bit lines and the source lines in a forming process. A first connection length along the bit lines and the source lines between the first memory cells and the driver is longer than a second connection length along the bit lines and the source lines between the second memory cells and the driver. The forming process is performed to the first memory cells before the forming process is performed to the second memory cells. A first value of the forming voltage provided to the first memory cells is less than a second value of the forming voltage provided to the second memory cells.

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

The present disclosure relates to a method for accessing memory cells comprising: applying an increasing read voltage with a first polarity to the plurality of memory cells; counting a number of switching memory cells in the plurality based on the applying the increasing read voltage; applying a first read voltage with the first polarity based on the number of switched memory cells reaching a threshold number; applying a second read voltage with a second polarity opposite to the first polarity; and determining that a memory cell in the plurality of memory cells has a first logic value based on the memory cell having switched during one of the applying the increasing read voltage and the applying the first read voltage or based on the memory cell not having switched during the applying the second read voltage. A related system is also disclosed.

Disclosed are a self-healing memory device including a lower electrode; a polymer nanocomposite layer formed on the lower electrode, wherein, when a structural defect occurs, the polymer nanocomposite layer repairs the structural defect and restores a memory function damaged due to the structural defect through a self-healing mechanism characterized by movement of a polymer material and hydrogen bonding; and an upper electrode formed on the polymer nanocomposite layer and a method of manufacturing the self-healing memory device.

An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.

A memristor-based circuit includes a voltage generator that applies a series of voltage pulses to a memristor to progressively change the resistance of the memristor. A comparator: receives an input electrical value; receives an electrical value based on the resistance of the memristor; compares the received values; and, based on the comparison, enables the application of the voltage pulses to the memristor by the voltage generator until a defined condition is satisfied. This circuit can be used to enable the memristor to be programmed to a desired resistance value, such as for use as a non-volatile memory. It can also enable the resistance of one memristor to be replicated to another memristor. By counting the number of applied voltage pulses, the circuit can be used as an encoder or analog-to-digital converter. Other variants of the circuit enable construction of a decoder or digital-to-analog converter, and an authentication circuit.

A semiconductor memory may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer separated from the first electrode layer, wherein the first and second electrode layers are coupled to receive a voltage applied to the first and second electrode layers; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and configured to store data and operable to disconnect or connect a conducting path between the first electrode layer and the second electrode layer, to respond to the voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes an insulating material layer, a first dopant that creates a shallow trap providing a path for conductive carriers in the insulating material layer, and a second dopant that is movable in the insulating material layer according to a polarity of the voltage applied to the first and second electrode layers.

Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.

A memristor-based circuit includes a voltage generator that applies a series of voltage pulses to a memristor to progressively change the resistance of the memristor. A comparator: receives an input electrical value; receives an electrical value based on the resistance of the memristor; compares the received values; and, based on the comparison, enables the application of the voltage pulses to the memristor by the voltage generator until a defined condition is satisfied. This circuit can be used to enable the memristor to be programmed to a desired resistance value, such as for use as a non-volatile memory. It can also enable the resistance of one memristor to be replicated to another memristor. By counting the number of applied voltage pulses, the circuit can be used as an encoder or analog-to-digital converter. Other variants of the circuit enable construction of a decoder or digital-to-analog converter, and an authentication circuit.

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.