Disclosed is a nonvolatile memory device including a plurality of memory cells operable to store data, each memory cell structured to include a resistance change layer exhibiting different resistance states with different resistance values for representing data, a write circuit suitable for generating a write pulse in a write mode to write data in a memory cell of the plurality of memory cells, and a read circuit suitable for generating a read pulse in a read mode to read data from a memory cell of the plurality of memory cells, wherein the memory cells are each structured to be operable in writing or reading data when a range of a voltage level change of the read pulse corresponding to a pulse width change of the read pulse is within a range of a voltage level change of the write pulse corresponding to a pulse width change of the write pulse.

According to one embodiment, a memory device includes a memory cell including a resistance change memory portion and a switching portion, and a voltage applying circuit carrying out, at a time of writing data to the memory cell, an operation of applying a voltage of a first polarity to the memory cell and applying a first voltage to the memory cell, an operation of applying a voltage of a second polarity to the memory cell and applying a second voltage to the memory cell, an operation of applying a voltage of the first polarity to the memory cell and applying a third voltage to the memory cell, or an operation of applying a voltage of the second polarity to the memory cell and applying a fourth voltage to the memory cell.

An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

A memory circuit including cells connected in rows and in columns, each cell including a programmable resistive element and a control transistor, the memory circuit further including a control circuit capable of, during a cell programming phase: applying a first voltage to a control conductive track of the column including the cell; applying a second voltage to the first control conductive track of the row including the cell; applying a third voltage capable of turning on the cell control transistor to a second row control conductive track including the cell; and applying a fourth voltage capable of turning off the control transistors to the control conductive tracks of columns which do not include the cell.

A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

A method for improving the stability of a resistive change cell is disclosed. The stability of a resistive change memory cell-that is, the tendency of the resistive change memory cell to retain its programmed resistive state-may, in certain applications, be compromised if the cell is programmed into an unstable or metastable state. In such applications, a programming method using bursts of sub-pulses within a pulse train is used to drive the resistive change cell material into a stable state during the programming operation, reducing resistance drift over time within the cell.

To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive random access memory (ReRAM) array is provided. The ReRAM array includes a plurality of memory cells each comprising resistive memory material formed into a layer of a substrate, with resistance properties of the resistive memory material corresponding to data bits stored by the memory cells. The ReRAM array also includes a plurality of interconnect features each comprising conductive material between adjacent memory cells formed into the layer of the substrate, and gate portions coupled onto the memory cells and configured to individually alter the resistance properties of the resistive memory material of associated memory cells responsive to at least voltages applied to the gate portions.