A memory cell, an integrated circuit and method of manufacturing the same are provided. The memory device includes a substrate, gate layers and insulating layers, an isolation column, a channel layer, a first conductive feature, a second conductive feature, a storage layer and a pair of isolation structures. The isolation column extends through the gate layers and the insulating layers along a first direction. The channel layer laterally covers the isolation column. The first conductive feature and second conductive feature extend along the first direction and adjacent to the isolation column. The storage layer is disposed between the gate layers and the channel layer. The pair of isolation structures extends along the first direction. The pair of isolation structures includes a first isolation structure disposed between the first conductive feature and the gate layers, and a second isolation structure disposed between the second conductive feature and the gate layers.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.

An interconnect for a semiconductor device includes: a carrier; a UV programmable chip mounted on the carrier using a first array of solder connections; a UV light source mounted on the carrier using a second array of solder connections, the UV light source being in optical communication with the UV programmable chip; and a plurality of transmission lines extending on or through the carrier and providing electrical communication between the UV programmable chip and the UV light source.

A semiconductor device capable of shortening an erasing time and suppressing deterioration of retention characteristics is provided. A semiconductor device includes: a semiconductor substrate having a main surface; a gate insulating film formed on the main surface; and a gate electrode formed on the gate insulating film. The gate insulating film includes a first silicon nitride film, and a first silicon oxide film arranged between the main surface and the first silicon nitride film and in contact with the first silicon nitride film. A Si—Si bond is formed in a boundary portion between the first silicon oxide film first silicon nitride film.

The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.

A deep neural network based on analog FLASH computing array, includes a number of computing arrays, a number of subtractors, a number of activation circuit units and a number of integral-recognition circuit units. The computing array includes a number of computing units, a number of word lines, a plurality number of bit lines and a number of source lines. Each of the computing units includes a FLASH cell. The gate electrodes of the FLASH cells in the same column are connected to the same word line. The source electrodes of the FLASH cells in the same column are connected to the same source line, and the drain electrodes of the FLASH cells in the same row are connected to the same bit line. Each of the subtractors includes a positive terminal, a negative terminal and an output terminal.

An ephemeral peripheral system includes an ephemeral memory system and controller circuit for securing user data for a smartphone application. Different secure operating modes are provided for customizing user security requirements across end-to-end communications links, including in exchanges of electronic data between smartphone devices.

A nonvolatile storage element includes a substrate; a gate region having a charge holding region and an insulator surrounding an entire surface of the charge holding region; a drain region formed in one of both sides of a lower portion of the gate region; and a source region formed in another one of both the sides. A halogen is distributed in the insulator to cover an entire surface of an upper surface of the charge holding region.

Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.