A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, wordlines coupled with first and second pillars. Control logic is to cause: wordlines to be discharged after a program pulse is applied to selected wordline; a supply voltage be applied to second data line to cause a voltage of second pillar to float; a ground voltage be applied to first data line to inhibit soft erase via first pillar; unselected wordlines be charged to boost channel voltages in memory cells coupled with the second pillar; and one of the ground voltage or a negative voltage be applied to the selected wordline to increase soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be erased.

A memory device includes a first bit line configured to supply a first bit line bias voltage, a memory cell transistor having a first operating voltage, a selection transistor having a second operating voltage and configured to control the supply of the first bit line bias voltage to a source of the memory cell transistor, and a second bit line connected to a drain of the memory cell transistor. A level of the first operating voltage is about equal to a level of the second operating voltage.

A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.

A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.

Disclosed is an electronic device which includes processing elements arranged in rows and columns, word lines connected with the rows of the processing elements, bit lines connected with the columns of the processing elements, body lines connected with the columns of the processing elements, and source lines connected with the rows of the processing elements. Each of the processing elements includes a first terminal connected with a corresponding bit line of the bit lines, a second terminal connected with a corresponding source line of the source lines, a control gate connected with a corresponding word line of the word lines, a floating gate between the control gate and a body, a body terminal connected with a corresponding body line of the body lines, and a capacitive element between the floating gate and the corresponding bit line.

A reading method for a non-volatile memory device, includes performing a normal read operation using a default read level in response to a first read command; and performing a read operation using a multiple on-chip valley search (OVS) sensing operation in response to a second read command, when read data read in the normal read operation are uncorrectable.

A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

An embedded flash memory and an operation method thereof is provided. The embedded flash memory includes a memory cell array comprising a plurality of memory cells, an automatic verification controller comprising: a TRIM calibration configured to provide a write voltage, and a time controller configured to control a write time, and a high voltage generator configured to provide the write voltage to the memory cell array, an input buffer configured to store input data, a sense amplifier configured to generate read data from the memory cell array, and a data comparator configured to compare the read data with the input data.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.